Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Cell Design in Prolog

Ashar A. Butt

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-86-286
February 1986

http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-286.pdf

Automatic synthesis of CMOS cells is considered in the programming idiom of Prolog. Cells are specified at the boolean level using Prolog structures and a layout of the cell is generated at the CIF (Caltech Intermediate Format) level.

A set of Prolog programs has been developed for this purpose. A three pass approach has been taken. The first pass takes boolean equations and transforms it into a net-list of transistors corresponding to static CMOS design style. The second pass (implemented by Rick Mcgeer) takes the transistor net-list and lays it out on a virtual grid in the style of a Gate Matrix. The third pass takes the sticks layout on the virtual grid and compacts it onto a lambda grid to produce CIF code.

A few test cells have been passed through this cell synthesizer. Example cases include an exclusive-nor gate, a cross-coupled nand gate pair, a hand laid out exclusive-nor gate passed through the compactor only.


BibTeX citation:

@techreport{Butt:CSD-86-286,
    Author = {Butt, Ashar A.},
    Title = {Cell Design in Prolog},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1986},
    Month = {Feb},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/5377.html},
    Number = {UCB/CSD-86-286},
    Abstract = {Automatic synthesis of CMOS cells is considered in the programming idiom of Prolog. Cells are specified at the boolean level using Prolog structures and a layout of the cell is generated at the CIF (Caltech Intermediate Format) level.  <p>  A set of Prolog programs has been developed for this purpose. A three pass approach has been taken. The first pass takes boolean equations and transforms it into a net-list of transistors corresponding to static CMOS design style. The second pass (implemented by Rick Mcgeer) takes the transistor net-list and lays it out on a virtual grid in the style of a Gate Matrix. The third pass takes the sticks layout on the virtual grid and compacts it onto a lambda grid to produce CIF code.  <p>  A few test cells have been passed through this cell synthesizer. Example cases include an exclusive-nor gate, a cross-coupled nand gate pair, a hand laid out exclusive-nor gate passed through the compactor only.}
}

EndNote citation:

%0 Report
%A Butt, Ashar A.
%T Cell Design in Prolog
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-86-286
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/5377.html
%F Butt:CSD-86-286