Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

The Memory Architecture and the Cache and Memory Management Unit for the Fairchild CLIPPER Processor

James Cho, Alan Jay Smith and Howard Sachs

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-86-289
April 1986

http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-289.pdf

The Fairchild CLIPPER is a new high-performance three chip module consisting of a microprocessor chip and two cache and memory management (CAMMU) chips, mounted on a small PC board. CLIPPER implements a new instruction set architecture which has been designed for high performance, convenient programmability, broad functionality and sufficient architectural "openness" to permit future evolution and a variety of implementations.

The CLIPPER memory architecture is a separate 32 bit logical address space for each of the user and supervisor, with facilities for transferring information from one to the other. Virtual memory support is provided by a memory management unit on each CAMMU, each of which includes a translator that maps 32 bit virtual addresses through a two level page table to 4096 byte pages, and a 2-way set associative 128 entry TLB. There is a 4096 byte cache for each of instructions and data; it is organized as two way set associative with 16-byte lines and with LRU replacement within each set. The caching policy (write-through, copy back, non-cacheable) may be specified on a page basis, as may the protection modes (read, write, execute, by user and supervisor). The bus protocol and interface provides a mechanism to maintain cache consistency when the bus is shared by multiple processors and I/O devices with overlapping physical address spaces. There is a translator, cache and TLB implemented on each of the two CAMMU (cache and memory management unit) chips.

In this paper, we discuss, in some detail, the memory architecture and the cache and memory management units of the Fairchild CLIPPER. Timing for operations and performance estimates are provided. There is some discussion as well for the various implementation decisions and the tradeoffs involved.


BibTeX citation:

@techreport{Cho:CSD-86-289,
    Author = {Cho, James and Smith, Alan Jay and Sachs, Howard},
    Title = {The Memory Architecture and the Cache and Memory Management Unit for the Fairchild CLIPPER Processor},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1986},
    Month = {Apr},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/5193.html},
    Number = {UCB/CSD-86-289},
    Abstract = {The Fairchild CLIPPER is a new high-performance three chip module consisting of a microprocessor chip and two cache and memory management (CAMMU) chips, mounted on a small PC board. CLIPPER implements a new instruction set architecture which has been designed for high performance, convenient programmability, broad functionality and sufficient architectural "openness" to permit future evolution and a variety of implementations.  <p>  The CLIPPER memory architecture is a separate 32 bit logical address space for each of the user and supervisor, with facilities for transferring information from one to the other. Virtual memory support is provided by a memory management unit on each CAMMU, each of which includes a translator that maps 32 bit virtual addresses through a two level page table to 4096 byte pages, and a 2-way set associative 128 entry TLB. There is a 4096 byte cache for each of instructions and data; it is organized as two way set associative with 16-byte lines and with LRU replacement within each set. The caching policy (write-through, copy back, non-cacheable) may be specified on a page basis, as may the protection modes (read, write, execute, by user and supervisor). The bus protocol and interface provides a mechanism to maintain cache consistency when the bus is shared by multiple processors and I/O devices with overlapping physical address spaces. There is a translator, cache and TLB implemented on each of the two CAMMU (cache and memory management unit) chips.  <p>  In this paper, we discuss, in some detail, the memory architecture and the cache and memory management units of the Fairchild CLIPPER. Timing for operations and performance estimates are provided. There is some discussion as well for the various implementation decisions and the tradeoffs involved.}
}

EndNote citation:

%0 Report
%A Cho, James
%A Smith, Alan Jay
%A Sachs, Howard
%T The Memory Architecture and the Cache and Memory Management Unit for the Fairchild CLIPPER Processor
%I EECS Department, University of California, Berkeley
%D 1986
%@ UCB/CSD-86-289
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/5193.html
%F Cho:CSD-86-289