Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Line (Block) Size Choice for CPU Cache Memories

Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-85-239
June 1985

The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, we study the factors that relate to the selection of a cache line size. Our primary focus is on the cache miss ratio, but we also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc. The behavior of the cache miss ratio as a function of line size is examined carefully through the use of trace driven simulation, using 27 traces from 5 different machine architectures. The change in cache miss ratio as the line size varies is found to be relatively stable across workloads, and tables of this function are presented for instruction caches, data caches, and unified caches. An empirical mathematical fit is obtained. This function is used to extend previously published design target miss ratios to cover line sizes from 4 bytes to 128 bytes and cache sizes from 32 bytes to 32 Kbytes; design target miss ratios are to be used to guide new machine designs. Mean delays per memory reference and memory (bus) traffic rates are computed as a function of line and cache size, and memory access time parameters. We find that for high performance microprocessor designs, line sizes in the range 16-64 bytes seem best; shorter line sizes yield high delays due to memory latency, although they reduce memory traffic somewhat. Longer line sizes are suitable for mainframes because of the higher bandwidth to main memory.


BibTeX citation:

@techreport{Smith:CSD-85-239,
    Author = {Smith, Alan Jay},
    Title = {Line (Block) Size Choice for CPU Cache Memories},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1985},
    Month = {Jun},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6071.html},
    Number = {UCB/CSD-85-239},
    Abstract = {The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, we study the factors that relate to the selection of a cache line size. Our primary focus is on the cache miss ratio, but we also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc. The behavior of the cache miss ratio as a function of line size is examined carefully through the use of trace driven simulation,  using 27 traces from 5 different machine architectures. The change in cache miss ratio as the line size varies is found to be relatively stable across workloads, and tables of this function are presented for instruction caches, data caches, and unified caches. An empirical mathematical fit is obtained. This function is used to extend previously published design target miss ratios to cover line sizes from 4 bytes to 128 bytes and cache sizes from 32 bytes to 32 Kbytes; design target miss ratios are to be used to guide new machine designs. Mean delays per memory reference and memory (bus) traffic rates are computed as a function of line and cache size, and memory access time parameters. We find that for high performance microprocessor designs, line sizes in the range 16-64 bytes seem best; shorter line sizes yield high delays due to memory latency, although they reduce memory traffic somewhat. Longer line sizes are suitable for mainframes because of the higher bandwidth to main memory.}
}

EndNote citation:

%0 Report
%A Smith, Alan Jay
%T Line (Block) Size Choice for CPU Cache Memories
%I EECS Department, University of California, Berkeley
%D 1985
%@ UCB/CSD-85-239
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6071.html
%F Smith:CSD-85-239