Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Cache Evaluation and the Impact of Workload Choice

Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-85-229
1985

http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/CSD-85-229.pdf

The selection of the "best" parameters for a cache design, such as size, mapping algorithm, fetch algorithm, line size, etc., is dependent on the expected workload. Similarly, the machine performance is sensitive to the cache performance which itself depends on the workload. Most cache designers have been greatly handicapped in their designs by the lack of realistic cache performance estimates. Published research generally presents data which is unrealistic in some respects, and available traces are often not representative. In this paper, we present measurements from a very wide variety of traces: there are 49 traces, taken from 6 machine architectures, (370, 360, VAX, M68000, Z8000, CDC 6400), coded in 7 source languages. Statistics are shown for miss ratios, the effectiveness of prefetching in terms of both miss ratio and its effect on bus traffic, the frequency of writes, reads and instruction fetches, and the frequency of branches. Some general observations are made and a "design estimate" set of miss ratios are proposed. Some "fudge" factors are proposed by which statistics for workloads for one machine architecture can be used to estimate corresponding parameters for another (as yet unrealized) architecture.


BibTeX citation:

@techreport{Smith:CSD-85-229,
    Author = {Smith, Alan Jay},
    Title = {Cache Evaluation and the Impact of Workload Choice},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1985},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5938.html},
    Number = {UCB/CSD-85-229},
    Abstract = {The selection of the "best" parameters for a cache design, such as size, mapping algorithm, fetch algorithm, line size, etc., is dependent on the expected workload. Similarly, the machine performance is sensitive to the cache performance which itself depends on the workload. Most cache designers have been greatly handicapped in their designs by the lack of realistic cache performance estimates.  Published research generally presents data which is unrealistic in some respects, and available traces are often not representative. In this paper, we present measurements from a very wide variety of traces: there are 49 traces, taken from 6 machine architectures, (370, 360, VAX, M68000, Z8000, CDC 6400), coded in 7 source languages. Statistics are shown for miss ratios, the effectiveness of prefetching in terms of both miss ratio and its effect on bus traffic, the frequency of writes, reads and instruction fetches, and the frequency of branches.  Some general observations are made and a "design estimate" set of miss ratios are proposed. Some "fudge" factors are proposed by which statistics for workloads for one machine architecture can be used to estimate corresponding parameters for another (as yet unrealized) architecture.}
}

EndNote citation:

%0 Report
%A Smith, Alan Jay
%T Cache Evaluation and the Impact of Workload Choice
%I EECS Department, University of California, Berkeley
%D 1985
%@ UCB/CSD-85-229
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5938.html
%F Smith:CSD-85-229