TLB For Free: In-Cache Address Translation For A Multiprocessor Workstation
Scott Allen Ritchie
EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-85-233
May 1985
http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/CSD-85-233.pdf
In the design of SPUR, a high-performance multiprocessor workstation, the need for large "snooping" caches suggests a new approach to virtual address translation. By performing this translation in each processor's virtual cache, the need for separate translation lookaside buffers is eliminated. Trace-driven simulations show that normal cache behavior is only minimally effected, and that unless an extremely large and complex TLB were built, using a separate device would actually reduce system performance.
BibTeX citation:
@techreport{Ritchie:CSD-85-233,
Author = {Ritchie, Scott Allen},
Title = {TLB For Free: In-Cache Address Translation For A Multiprocessor Workstation},
Institution = {EECS Department, University of California, Berkeley},
Year = {1985},
Month = {May},
URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5936.html},
Number = {UCB/CSD-85-233}
}
EndNote citation:
%0 Report %A Ritchie, Scott Allen %T TLB For Free: In-Cache Address Translation For A Multiprocessor Workstation %I EECS Department, University of California, Berkeley %D 1985 %@ UCB/CSD-85-233 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5936.html %F Ritchie:CSD-85-233