Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses

Randy H. Katz, Susan J. Eggers, Garth A. Gibson, Paul Mark Hansen, Mark Donald Hill, J. M. Pendleton, Scott Allen Ritchie, George S. Taylor, David A. Wood and David A. Patterson

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-85-221
January 1985

http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/CSD-85-221.pdf

We describe the memory system design of a tightly-coupled multiprocessor. Each processor node consists of a VLSI RISC processor, a VLSI cache controller, cache data RAMs, and a standard bus. We show that adequate performance can be achieved only if the processor has an on-chip instruction buffer and a large (64KB-256KB) local instruction and data cache. Ways of reducing the number of cache tags and the effects of various implementation alternatives for where to perform virtual memory translation are also described.


BibTeX citation:

@techreport{Katz:CSD-85-221,
    Author = {Katz, Randy H. and Eggers, Susan J. and Gibson, Garth A. and Hansen, Paul Mark and Hill, Mark Donald and Pendleton, J. M. and Ritchie, Scott Allen and Taylor, George S. and Wood, David A. and Patterson, David A.},
    Title = {Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1985},
    Month = {Jan},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5926.html},
    Number = {UCB/CSD-85-221},
    Abstract = {We describe the memory system design of a tightly-coupled multiprocessor. Each processor node consists of a VLSI RISC processor, a VLSI cache controller, cache data RAMs, and a standard bus.  We show that adequate performance can be achieved only if the processor has an on-chip instruction buffer and a large (64KB-256KB) local instruction and data cache. Ways of reducing the number of cache tags and the effects of various implementation alternatives for where to perform virtual memory translation are also described.}
}

EndNote citation:

%0 Report
%A Katz, Randy H.
%A Eggers, Susan J.
%A Gibson, Garth A.
%A Hansen, Paul Mark
%A Hill, Mark Donald
%A Pendleton, J. M.
%A Ritchie, Scott Allen
%A Taylor, George S.
%A Wood, David A.
%A Patterson, David A.
%T Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses
%I EECS Department, University of California, Berkeley
%D 1985
%@ UCB/CSD-85-221
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5926.html
%F Katz:CSD-85-221