Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

BBL.2 User's Manual

N-P. Chen, C-C. Chen, C-P. Hsu, H.H. Chen, Ernest S. Kuh and M.M. Sadowska

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M85/2
1985

http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/ERL-85-2.pdf

BBL is an automatic layout system for placement and routing in VLSI design. The building-block modules are assumed to be rectilinear, and two layers of interconnection are used. The placement system of BBL consists of three major phases: the bottom-up phase to handle the highly connected module pairs and clusters, the top-down phase to deal with the size and the shape of modules, and the trade-off phase to minimize the global connections as well as the overall chip area. The current placement system can only handle rectangular modules. The routing system of BBL includes prerouting analysis, global routing, and detailed routing. The purpose of prerouting analysis is to allocated routing space if the original placement is not desirable. In global routing, a Steiner-Tree-On-Graph algorithm is used to assign each net a specific route without actually embedding it. Nets which belong to a common bus will be assigned the same global route. In detailed routing, channel router and switch-box router are used to do the track assignment. Power and ground nets may have different wire widths, and they will be routed on one layer unless they cross each other. Since modules can be shifted during the routing process, 100% routing completion is always guaranteed. Currently, BBL runs on a VAX 11/780 under 4.2 Berkeley UNIX. HP 2648A terminal is used as the graphics display, and the final layout will be generated in CIF format. The entire BBL system is implemented in C language, except the channel router, which is written in PASCAL. Many examples from industry have been tested. Experimental results show that the chip area can be reduced by 10-25% with the BBL layout. For an AMI chip with 33 modules, 132 nets, and 440 pins, it takes 69 CPU seconds to finish the placement and 5.5 minutes to complete the routing.


BibTeX citation:

@techreport{Chen:M85/2,
    Author = {Chen, N-P. and Chen, C-C. and Hsu, C-P. and Chen, H.H. and Kuh, Ernest S. and Sadowska, M.M.},
    Title = {BBL.2 User's Manual},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1985},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/440.html},
    Number = {UCB/ERL M85/2},
    Abstract = {BBL is an automatic layout system for placement and routing in VLSI
design.  The building-block modules are assumed to be rectilinear, 
and two layers of interconnection are used.  The placement system
of BBL consists of three major phases: the bottom-up phase to handle
the highly connected module pairs and clusters, the top-down phase to
deal with the size and the shape of modules, and the trade-off phase
to minimize the global connections as well as the overall chip area.
The current placement system can only handle rectangular modules.
The routing system of BBL includes prerouting analysis, global
routing, and detailed routing.  The purpose of prerouting analysis
is to allocated routing space if the original placement is not
desirable.  In global routing, a Steiner-Tree-On-Graph algorithm is
used to assign each net a specific route without actually embedding
it.  Nets which belong to a common bus will be assigned the same
global route.  In detailed routing, channel router and switch-box
router are used to do the track assignment.  Power and ground nets
may have different wire widths, and they will be routed on one layer
unless they cross each other.  Since modules can be shifted during
the routing process, 100% routing completion is always guaranteed.

Currently, BBL runs on a VAX 11/780 under 4.2 Berkeley UNIX.
HP 2648A terminal is used as the graphics display, and the final
layout will be generated in CIF format.  The entire BBL system
is implemented in C language, except the channel router, which is
written in PASCAL.  Many examples from industry have been tested.
Experimental results show that the chip area can be reduced by 10-25%
with the BBL layout.  For an AMI chip with 33 modules, 132 nets,
and 440 pins, it takes 69 CPU seconds to finish the placement and
5.5 minutes to complete the routing.}
}

EndNote citation:

%0 Report
%A Chen, N-P.
%A Chen, C-C.
%A Hsu, C-P.
%A Chen, H.H.
%A Kuh, Ernest S.
%A Sadowska, M.M.
%T BBL.2 User's Manual
%I EECS Department, University of California, Berkeley
%D 1985
%@ UCB/ERL M85/2
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/440.html
%F Chen:M85/2