Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Design and Implementation of An Integrated Snooping Data Cache

Gaetano Borriello, Susan J. Eggers, Randy H. Katz, Harry McKinley, Charles Perkins, Walter Scott, Robert Sheldon, Shaun Whalen and David A. Wood

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-84-199
September 1984

http://www.eecs.berkeley.edu/Pubs/TechRpts/1984/CSD-84-199.pdf

We describe the design and single chip implementation of a small data cache memory and associated controllers. The chip can be used as a building block of a multiprocessor system, positioned between the main memory bus and an individual processor. It implements an ownership-based cache consistency protocol. The chip has been designed to be interfaced to the MultiBus system bus and the Motorola 68000 processor. In this paper, we present our cache consistency protocol and its evaluation, and the chip architecture, design decisions, and implementation details.


BibTeX citation:

@techreport{Borriello:CSD-84-199,
    Author = {Borriello, Gaetano and Eggers, Susan J. and Katz, Randy H. and McKinley, Harry and Perkins, Charles and Scott, Walter and Sheldon, Robert and Whalen, Shaun and Wood, David A.},
    Title = {Design and Implementation of An Integrated Snooping Data Cache},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1984},
    Month = {Sep},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1984/5947.html},
    Number = {UCB/CSD-84-199},
    Abstract = {We describe the design and single chip implementation of a small data cache memory and associated controllers. The chip can be used as a building block of a multiprocessor system, positioned between the main memory bus and an individual processor. It implements an ownership-based cache consistency protocol. The chip has been designed to be interfaced to the MultiBus system bus and the Motorola 68000 processor. In this paper, we present our cache consistency protocol and its evaluation, and the chip architecture, design decisions, and implementation details.}
}

EndNote citation:

%0 Report
%A Borriello, Gaetano
%A Eggers, Susan J.
%A Katz, Randy H.
%A McKinley, Harry
%A Perkins, Charles
%A Scott, Walter
%A Sheldon, Robert
%A Whalen, Shaun
%A Wood, David A.
%T Design and Implementation of An Integrated Snooping Data Cache
%I EECS Department, University of California, Berkeley
%D 1984
%@ UCB/CSD-84-199
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1984/5947.html
%F Borriello:CSD-84-199