Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Iterated Timing Analysis and SPLICE1

R.A. Saleh

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M84/2
1984

http://www.eecs.berkeley.edu/Pubs/TechRpts/1984/ERL-84-2.pdf

SPLICE1 is a mixed-mode simulation program for large-scale integrated circuits. It performs concurrent electrical and logic simulation using event-driven selective-trace techniques. The electrical analysis uses a new algorithm, called Iterated Timing Analysis (ITA), which performs accurate electrical waveform analysis much faster than SPICE2. The logic analysis features a new MOS-oriented state model and a fanout dependent delay model, and handles bidirectional transfer gates in a consistent manner. This report describes the new algorithms and the details of the implementation in SPLICE1.6. Program performance characteristics and a number of simulation results are also included.


BibTeX citation:

@techreport{Saleh:M84/2,
    Author = {Saleh, R.A.},
    Title = {Iterated Timing Analysis and SPLICE1},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1984},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1984/243.html},
    Number = {UCB/ERL M84/2},
    Abstract = {SPLICE1 is a mixed-mode simulation program for large-scale integrated
circuits.  It performs concurrent electrical and logic simulation
using event-driven selective-trace techniques.  The electrical
analysis uses a new algorithm, called Iterated Timing Analysis
(ITA), which performs accurate electrical waveform analysis much
faster than SPICE2.  The logic analysis features a new MOS-oriented
state model and a fanout dependent delay model, and handles
bidirectional transfer gates in a consistent manner.

This report describes the new algorithms and the details of the
implementation in SPLICE1.6.  Program performance characteristics
and a number of simulation results are also included.}
}

EndNote citation:

%0 Report
%A Saleh, R.A.
%T Iterated Timing Analysis and SPLICE1
%I EECS Department, University of California, Berkeley
%D 1984
%@ UCB/ERL M84/2
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1984/243.html
%F Saleh:M84/2