Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

The VLSI Circuitry of RISC I

James B. Peek

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-83-135
June 1983

http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/CSD-83-135.pdf

This paper describes the very large scale integrated circuitry and chip level architecture of RISC I, a Reduced Instruction Set Computer. RISC I is a single chip 32-bit microprocessor, designed with a simple, yet powerful architecture. Its major features include a 3 bus data path, a simple controller, and a 3 phase clock. The RISC I microprocessor, also known as RISC Gold, was implemented as part of the RISC project at the University of California at Berkeley during the winter and spring of 1981. The chip contains 44,500 transistors, and has been fabricated using 4 micron (minimum gate length) NMOS depletion load technology. Testing of the chip has shown that it is operational. It has been demonstrated running small programs.


BibTeX citation:

@techreport{Peek:CSD-83-135,
    Author = {Peek, James B.},
    Title = {The VLSI Circuitry of RISC I},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1983},
    Month = {Jun},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/6347.html},
    Number = {UCB/CSD-83-135},
    Abstract = {This paper describes the very large scale integrated circuitry and chip level architecture of RISC I, a Reduced Instruction Set Computer. RISC I is a single chip 32-bit microprocessor, designed with a simple, yet powerful architecture. Its major features include a 3 bus data path, a simple controller, and a 3 phase clock. The RISC I microprocessor, also known as RISC Gold, was implemented as part of the RISC project at the University of California at Berkeley during the winter and spring of 1981. The chip contains 44,500 transistors, and has been fabricated using 4 micron (minimum gate length) NMOS depletion load technology. Testing of the chip has shown that it is operational. It has been demonstrated running small programs.}
}

EndNote citation:

%0 Report
%A Peek, James B.
%T The VLSI Circuitry of RISC I
%I EECS Department, University of California, Berkeley
%D 1983
%@ UCB/CSD-83-135
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/6347.html
%F Peek:CSD-83-135