Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Reduced Instruction Set Computer Architectures for VLSI

Emmanuel-Manolis George Katevenis

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-83-141
October 1983

Integrated circuits offer compact and low-cost implementation of digital systems, and provide performance gains through their high-bandwidth on-chip communication. When this technology is used to build a general-purpose von Neumann processor, it is desirable to integrate as much functionality as possible on a single chip, so as to minimize off-chip communication. Even in Very Large Scale Integrated (VLSI) circuits, however, the transistors available on the limited chip area constitute a scarce resource when used for the implementation of a complete processor or even computer, and thus, they have to be used effectively. This dissertation shows that the recent trend in computer architecture towards instruction sets of increasing complexity leads to inefficient use of those scarce resources. We investigate the alternative of Reduced Instruction Set Computer (RISC) architectures which allow effective use of on-chip transistors in functional units that provide fast access to frequently used operands and instructions.

In this dissertation, the nature of general-purpose computations is studied, showing the simplicity of the operations usually performed and the high frequency of operand accesses, many of which are made to the few local scalar variables of procedures. The architecture of the RISC I and II processors is presented. They feature simple instructions and a large multi-window register file, whose overlapping windows are used for holding the arguments and local scalar variables of the most recently activated procedures. In the framework of the RISC project, which has been a large team effort at U. C. Berkeley for more than three years, a RISC II nMOS single-chip processor was implemented, in collaboration with R. Sherburne. Its microarchitecture is described and evaluated, followed by a discussion of the debugging and testing methods used. Future VLSI technology will allow the integration of larger systems on a single chip. The effective utilization of the additional transistors is considered, and it is proposed that they should be used in implementing specially organized instruction fetch-and-sequence units and data caches.

The architectural study and evaluation of RISC II, as well as its design, layout, and testing after fabrication, have shown the viability and the advantages of the RISC approach. The RISC II single-chip processor looks different from other popular commercial processors: it has been less total transistors, it spends only 10% of the chip area for control rather than one half to two thirds, and it required about five times less design and lay-out effort to get chips that work correctly and at speed on first silicon. And, on top of all that, RISC II executes integer, high level language programs significantly faster than these other processors made in similar technologies.

Advisor: Carlo H. Séquin


BibTeX citation:

@phdthesis{Katevenis:CSD-83-141,
    Author = {Katevenis, Emmanuel-Manolis George},
    Title = {Reduced Instruction Set Computer Architectures for VLSI},
    School = {EECS Department, University of California, Berkeley},
    Year = {1983},
    Month = {Oct},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/5779.html},
    Number = {UCB/CSD-83-141},
    Abstract = {Integrated circuits offer compact and low-cost implementation of digital systems, and provide performance gains through their high-bandwidth on-chip communication. When this technology is used to build a general-purpose von Neumann processor, it is desirable to integrate as much functionality as possible on a single chip, so as to minimize off-chip communication. Even in Very Large Scale Integrated (VLSI) circuits, however, the transistors available on the limited chip area constitute a scarce resource when used for the implementation of a complete processor or even computer, and thus, they have to be used effectively. This dissertation shows that the recent trend in computer architecture towards instruction sets of increasing complexity leads to inefficient use of those scarce resources. We investigate the alternative of Reduced Instruction Set Computer (RISC) architectures which allow effective use of on-chip transistors in functional units that provide fast access to frequently used operands and instructions.  <p>  In this dissertation, the nature of general-purpose computations is studied, showing the simplicity of the operations usually performed and the high frequency of operand accesses, many of which are made to the few local scalar variables of procedures.  The architecture of the RISC I and II processors is presented.  They feature simple instructions and a large multi-window register file, whose overlapping windows are used for holding the arguments and local scalar variables of the most recently activated procedures.  In the framework of the RISC project, which has been a large team effort at U. C. Berkeley for more than three years, a RISC II nMOS single-chip processor was implemented, in collaboration with R. Sherburne. Its microarchitecture is described and evaluated, followed by a discussion of the debugging and testing methods used. Future VLSI technology will allow the integration of larger systems on a single chip.  The effective utilization of the additional transistors is considered, and it is proposed that they should be used in implementing specially organized instruction fetch-and-sequence units and data caches.  <p>  The architectural study and evaluation of RISC II, as well as its design, layout, and testing after fabrication, have shown the viability and the advantages of the RISC approach. The RISC II single-chip processor looks different from other popular commercial processors: it has been less total transistors, it spends only 10% of the chip area for control rather than one half to two thirds, and it required about five times less design and lay-out effort to get chips that work correctly and at speed on first silicon. And, on top of all that, RISC II executes integer, high level language programs significantly faster than these other processors made in similar technologies.}
}

EndNote citation:

%0 Thesis
%A Katevenis, Emmanuel-Manolis George
%T Reduced Instruction Set Computer Architectures for VLSI
%I EECS Department, University of California, Berkeley
%D 1983
%@ UCB/CSD-83-141
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/5779.html
%F Katevenis:CSD-83-141