Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

PLEASURE: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays

Giovanni De Micheli and Alberto Sangiovanni-Vincentelli

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M82/57
1982

http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/ERL-82-57.pdf

Programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.


BibTeX citation:

@techreport{De Micheli:M82/57,
    Author = {De Micheli, Giovanni and Sangiovanni-Vincentelli, Alberto},
    Title = {PLEASURE: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1982},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/9615.html},
    Number = {UCB/ERL M82/57},
    Abstract = {Programmable logic arrays are important building blocks of VLSI
circuits and systems.  We address the problem of optimizing
the silicon area and the performances of large logic arrays.
In particular we describe a general method for compacting a logic
array defined as multiple row and column folding and we address
the problem of interconnecting a PLA to the outside circuitry.
We define a constrained optimization problem to achieve minimal
silicon area occupation with constrained positions of electrical
inputs and outputs.  We present a new computer program, PLEASURE,
which implements several algorithms for multiple and/or constrained
PLA folding.}
}

EndNote citation:

%0 Report
%A De Micheli, Giovanni
%A Sangiovanni-Vincentelli, Alberto
%T PLEASURE: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays
%I EECS Department, University of California, Berkeley
%D 1982
%@ UCB/ERL M82/57
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/9615.html
%F De Micheli:M82/57