Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Design and Implementation of RISC I

Carlo H. Séquin and David A. Patterson

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-82-106
October 1982

http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/CSD-82-106.pdf

The Reduced Instruction Set Computer (RISC) is an architecture particularly well suited for implementation as a single-chip VLSI computer. It demonstrates that by a judicious choice of a small set of instructions and the design of a corresponding micro-architecture, one can obtain a machine with high throughput. The limited number of instructions and addressing modes leads to a small control section and to a short machine cycle time. Such a machine also requires a much smaller layout effort and thus leads to a shorter design cycle.

Such a RISC architecture has been implemented at U. C. Berkeley as part of a four quarter sequence of graduate courses in which students propose and evaluate architectural ideas, design LSI components, integrate those components into a VLSI chip, and finally test the actual chip. The CAD and testing environment in which this chip was created is also described.


BibTeX citation:

@techreport{Séquin:CSD-82-106,
    Author = {Séquin, Carlo H. and Patterson, David A.},
    Title = {Design and Implementation of RISC I},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1982},
    Month = {Oct},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/5449.html},
    Number = {UCB/CSD-82-106},
    Abstract = {The Reduced Instruction Set Computer (RISC) is an architecture particularly well suited for implementation as a single-chip VLSI computer. It demonstrates that by a judicious choice of a small set of instructions and the design of a corresponding micro-architecture, one can obtain a machine with high throughput. The limited number of instructions and addressing modes leads to a small control section and to a short machine cycle time.  Such a machine also requires a much smaller layout effort and thus leads to a shorter design cycle.  <p>  Such a RISC architecture has been implemented at U. C. Berkeley as part of a four quarter sequence of graduate courses in which students propose and evaluate architectural ideas, design LSI components, integrate those components into a VLSI chip, and finally test the actual chip. The CAD and testing environment in which this chip was created is also described.}
}

EndNote citation:

%0 Report
%A Séquin, Carlo H.
%A Patterson, David A.
%T Design and Implementation of RISC I
%I EECS Department, University of California, Berkeley
%D 1982
%@ UCB/CSD-82-106
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1982/5449.html
%F Séquin:CSD-82-106