# The Simulation of Large-Scale Integrated Circuits

### A. Richard Newton

###
EECS Department

University of California, Berkeley

Technical Report No. UCB/ERL M78/52

1978

### http://www.eecs.berkeley.edu/Pubs/TechRpts/1978/ERL-78-52.pdf

Electronic circuit simulation programs can accurately predict voltage and current waveforms for small integrated circuits but as the size of the circuit increases, e.g. for Large-Scale Integrated (LSI) Circuits involving more than 10000 devices, the cost and memory requirements of such analyses become prohibitive.

Logic simulators can be used for LSI digital circuit evaluation and design if only first-order timing information based on user-specified logic gate delays is required. If voltage waveforms and calculated delays are important, a timing simulator may be used. In many circuits, however, there are critical paths or analog circuit blocks where more accurate circuit analysis is necessary.

This dissertation describes the hybrid simulation program SPLICE, developed for the analysis and design of LSI Metal-Oxide-Semiconductor (MOS) circuits. SPLICE allows the designer to choose the form of analysis best suited to each part of the circuit and logic, timing and circuit analyses are performed concurrently. The use of an event scheduling algorithm and selective-trace analysis allows the program to take advantage of the relatively low activity of LSI circuits to reduce the cost of the simulation.

SPLICE is between one and three orders of magnitude faster than a circuit simulation program, for comparable analysis accuracy, and requires less than ten percent of the data storage used in a circuit analysis. SPLICE is written in FORTRAN and is approximately 8000 statements long.

The algorithms and data structures used in SPLICE are described and a number of example simulations are included.

BibTeX citation:

@phdthesis{Newton:M78/52, Author = {Newton, A. Richard}, Title = {The Simulation of Large-Scale Integrated Circuits}, School = {EECS Department, University of California, Berkeley}, Year = {1978}, URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1978/9605.html}, Number = {UCB/ERL M78/52}, Abstract = {Electronic circuit simulation programs can accurately predict voltage and current waveforms for small integrated circuits but as the size of the circuit increases, e.g. for Large-Scale Integrated (LSI) Circuits involving more than 10000 devices, the cost and memory requirements of such analyses become prohibitive. Logic simulators can be used for LSI digital circuit evaluation and design if only first-order timing information based on user-specified logic gate delays is required. If voltage waveforms and calculated delays are important, a timing simulator may be used. In many circuits, however, there are critical paths or analog circuit blocks where more accurate circuit analysis is necessary. This dissertation describes the hybrid simulation program SPLICE, developed for the analysis and design of LSI Metal-Oxide-Semiconductor (MOS) circuits. SPLICE allows the designer to choose the form of analysis best suited to each part of the circuit and logic, timing and circuit analyses are performed concurrently. The use of an event scheduling algorithm and selective-trace analysis allows the program to take advantage of the relatively low activity of LSI circuits to reduce the cost of the simulation. SPLICE is between one and three orders of magnitude faster than a circuit simulation program, for comparable analysis accuracy, and requires less than ten percent of the data storage used in a circuit analysis. SPLICE is written in FORTRAN and is approximately 8000 statements long. The algorithms and data structures used in SPLICE are described and a number of example simulations are included.} }

EndNote citation:

%0 Thesis %A Newton, A. Richard %T The Simulation of Large-Scale Integrated Circuits %I EECS Department, University of California, Berkeley %D 1978 %@ UCB/ERL M78/52 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/1978/9605.html %F Newton:M78/52