Patents - Andreas Kuehlmann

Static analysis of computer code to determine impact of change to a code component upon a dependent code component
Murat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong and Tobias Welp
U.S. Patent 9,032,376. May 2015

General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software
Andreas Kuehlmann, Kenneth L. McMillan and Shmuel Sagiv
U.S. Patent 8,862,439. October 2014

Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software
Andreas Kuehlmann, Kenneth L. McMillan and Shmuel Sagiv
U.S. Patent 8,656,330. February 2014

Optimizing integrated circuit design through use of sequential timing information
Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich and Roberto Passerone
U.S. Patent 8,589,845. November 2013

Temporal decomposition for design and verification
Andreas Kuehlmann and Xiaoqun Du
U.S. Patent 8,418,101. April 2013

Temporal decomposition for design and verification
Andreas Kuehlmann and Xiaoqun Du
U.S. Patent 8,413,090. April 2013

Reducing critical cycle delay in an integrated circuit design through use of sequential slack
Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich and Roberto Passerone
U.S. Patent 8,307,316. June 2012

System, methods and apparatus for generation of simulation stimulus
Andreas Kuehlmann and Nathan Kitchen
U.S. Patent 8,020,125. September 2011

Reducing critical cycle delay in an integrated circuit design through use of sequential slack
Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich and Roberto Passerone
U.S. Patent 7,913,210. March 2011

Temporal decomposition for design and verification
Andreas Kuehlmann and Xiaoqun Du
U.S. Patent 7,900,173. March 2011

Optimizing integrated circuit design through use of sequential timing information
Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich and Roberto Passerone
U.S. Patent 7,743,354. June 2010

Data path and placement optimization in an integrated circuit through use of sequential timing information
Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich and Roberto Passerone
U.S. Patent 7,624,364. November 2009

Temporal decomposition for design and verification
Andreas Kuehlmann and Xiaoqun Du
U.S. Patent 7,596,770. September 2009

Optimization of combinational logic synthesis through clock latency scheduling
Christoph Albrecht, Andreas Kuehlmann, David Seibert and Sascha Richter
U.S. Patent 7,559,040. July 2009

Multi-domain clock skew scheduling
Andreas Kuehlmann, Kaushik Ravindran and Ellen Sentovich
U.S. Patent 7,296,246. November 2007

Framework for multiple-engine based verification tools for integrated circuits
Jason Raymond Baumgartner, Geert Janssen, Andreas Kuehlmann, Viresh Paruthi and Louise Helen Trevillyan
U.S. Patent 6,698,003. February 2004

Method and system for equivalence-checking combinatorial circuits using iterative binary-decision-diagram sweeping and structural satisfiability analysis
Malay Kumar Ganai, Geert Janssen, Florian Karl Krohm, Andreas Kuehlmann and Viresh Paruthi
U.S. Patent 6,473,884. October 2002

Method for performing functional comparison of combinational circuits
Andreas Kuehlmann and Florian Karl Krohm
U.S. Patent 6,035,107. March 2000

CMOS transistor network to gate level model extractor for simulation, verification and test generation
Sandip Kundu, Andreas Kuehlmann and Arvind Srinivasan
U.S. Patent 5,629,858. May 1997