Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

Patents - Tsu-Jae King Liu

Compact static memory cell with non-volatile storage capability
Tsu-Jae King Liu
U.S. Patent 7,266,010. September 2007

Method of IC production using corrugated substrate
Tsu-Jae King Liu and Victor Moroz
U.S. Patent 7,265,008. September 2007

Damascene process for use in fabricating semiconductor structures having micro/nano gaps
Hideki Takeuchi, Emmanuel P. Quevy, Tsu-Jae King Liu and Roger T. Howe
U.S. Patent 7,256,107. August 2007

Method of making adaptive negative differential resistance device
Tsu-Jae King Liu
U.S. Patent 7,254,050. August 2007

Segmented channel MOS transistor
Tsu-Jae King Liu
U.S. Patent 7,247,887. July 2007

Process for controlling performance characteristics of a negative differential resistance (NDR) device
Tsu-Jae King Liu
U.S. Patent 7,220,636. May 2007

Integrated circuit on corrugated substrate
Tsu-Jae King Liu and Victor Moroz
U.S. Patent 7,190,050. March 2007

Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
Tsu-Jae King
U.S. Patent 7,187,028. March 2007

Method of forming a negative differential resistance device
Tsu-Jae King
U.S. Patent 7,186,621. March 2007

Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET
Tsu-Jae King
U.S. Patent 7,186,619. March 2007

Dual work function CMOS gate technology based on metal interdiffusion
Igor Polishchuk, Pushkar Ranade, Tsu-Jae King and Chenming Hu
U.S. Patent 7,141,858. November 2006

Method of forming a negative differential resistance device
Tsu-Jae King
U.S. Patent 7,113,423. September 2006

CMOS compatible process for making a charge trapping device
Tsu-Jae King and David K. Y. Liu
U.S. Patent 7,109,078. September 2006

Negative differential resistance (NDR) elements and memory device using the same
Tsu-Jae King
U.S. Patent 7,098,472. August 2006

Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
Tsu-Jae King
U.S. Patent 7,095,659. August 2006

Ion beam extractor with counterbore
Qing Ji, Keith Standiford, Tsu-Jae King and Ka-Ngo Leung
U.S. Patent 7,084,407. August 2006

Charge trapping device
Tsu-Jae King and David K. Y. Liu
U.S. Patent 7,067,873. June 2006

Methods of testing/stressing a charge trapping device
Tsu-Jae King
U.S. Patent 7,060,524. June 2006

Charge trapping device and method of forming the same
Tsu-Jae King
U.S. Patent 7,015,536. March 2006

Two terminal silicon based negative differential resistance device
Tsu-Jae King
U.S. Patent 7,016,224. March 2006

Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
Tsu-Jae King
U.S. Patent 7,012,833. March 2006

Enhanced read and write methods for negative differential resistance (NDR) based memory device
Tsu-Jae King
U.S. Patent 7,012,842. March 2006

N-channel pull-up element and logic circuit
Tsu-Jae King
U.S. Patent 7,005,711. February 2006

Method of making memory cell utilizing negative differential resistance devices
Tsu-Jae King
U.S. Patent 6,990,016. January 2006

Process for controlling performance characteristics of a negative differential resistance (NDR) device
Tsu-Jae King
U.S. Patent 6,979,580. December 2005

Method of forming a negative differential resistance device
Tsu-Jae King
U.S. Patent 6,980,467. December 2005

CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,972,465. December 2005

Variable threshold semiconductor device and method of operating same
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,969,894. November 2005

Charge trapping pull up element
Tsu-Jae King
U.S. Patent 6,956,262. October 2005

Negative differential resistance load element
Tsu-Jae King
U.S. Patent 6,933,548. August 2005

Negative differential resistance (NDR) based memory device with reduced body effects
Tsu-Jae King
U.S. Patent 6,912,151. June 2005

Negative differential resistance pull up element
Tsu-Jae King
U.S. Patent 6,894,327. May 2005

Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects
Tsu-Jae King
U.S. Patent 6,864,104. March 2005

Negative differential resistance (NDR) memory cell with reduced soft error rate
Tsu-Jae King
U.S. Patent 6,861,707. March 2005

Multiple-thickness gate oxide formed by oxygen implantation
Ya-Chin King, Tsu-Jae King and Chenming Hu
U.S. Patent 6,855,994. February 2005

Negative differential resistance (NDR) memory device with reduced soft error rate
Tsu-Jae King
U.S. Patent 6,853,035. February 2005

Charge trapping device and method of forming the same
Tsu-Jae King
U.S. Patent 6,849,483. February 2005

Enhanced read and write methods for negative differential resistance (NDR) based memory device
Tsu-Jae King
U.S. Patent 6,847,562. January 2005

Adaptive negative differential resistance device
Tsu-Jae King
U.S. Patent 6,812,084. November 2004

Methods of testing/stressing a charge trapping device
Tsu-Jae King
U.S. Patent 6,806,117. October 2004

Dual work function CMOS gate technology based on metal interdiffusion
Igor Polishchuk, Pushkar Ranade, Tsu-Jae King and Chenming Hu
U.S. Patent 6,794,234. September 2004

Negative differential resistance (NDR) elements and memory device using the same
Tsu-Jae King
U.S. Patent 6,795,337. September 2004

Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET
Tsu-Jae King
U.S. Patent 6,754,104. June 2004

Multiple-thickness gate oxide formed by oxygen implantation
Ya-Chin King, Tsu-Jae King and Chenming Hu
U.S. Patent 6,753,229. June 2004

Negative differential resistance (NDR) element and memory with reduced soft error rate
Tsu-Jae King
U.S. Patent 6,727,548. April 2004

Memory cell using negative differential resistance field effect transistors
Tsu-Jae King
U.S. Patent 6,724,655. April 2004

Field effect transistor pull-up/load element
Tsu-Jae King
U.S. Patent 6,724,024. April 2004

Charge trapping device and method for implementing a transistor having a configurable threshold
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,700,115. March 2004

Method for configuring a device to include a negative differential resistance (NDR) characteristic
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,693,027. February 2004

Negative differential resistance (NDR) device and method of operating same
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,686,631. February 2004

Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode
Tsu-Jae King
U.S. Patent 6,686,267. February 2004

Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,680,245. January 2004

Method of operating a dual mode FET & logic circuit having negative differential resistance mode
Tsu-Jae King
U.S. Patent 6,664,601. December 2003

CMOS compatible process for making a tunable negative differential resistance (NDR) device
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,596,617. July 2003

Charge pump for negative differential resistance transistor
Tsu-Jae King
U.S. Patent 6,594,193. July 2003

Negative differential resistance (NDR) element and memory with reduced soft error rate
Tsu-Jae King
U.S. Patent 6,567,292. May 2003

Negative differential resistance field effect transistor (NDR-FET) and circuits using the same
Tsu-Jae King
U.S. Patent 6,559,470. May 2003

Dual mode FET & logic circuit having negative differential resistance mode
Tsu-Jae King
U.S. Patent 6,518,589. February 2003

CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,512,274. January 2003

Charge trapping device and method for implementing a transistor having a negative differential resistance mode
Tsu-Jae King and David K. Y. Liu
U.S. Patent 6,479,862. November 2002

Polycrystalline silicon-germanium films for micro-electromechanical systems application
Andrea Franke, Roger T. Howe and Tsu-Jae King
U.S. Patent 6,448,622. September 2002

FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu, Tsu-Jae King, Vivek Subramanian, Leland Chang, Xuejue Huang, Yang-Kyu Choi, Jakub Tadeusz Kedzierski, Nick Lindert, Jeffrey Bokor and Wen-Chin Lee
U.S. Patent 6,413,802. July 2002

Polycrystalline silicon germanium films for forming micro-electromechanical systems
Roger T. Howe, Andrea Franke and Tsu-Jae King
U.S. Patent 6,210,988. April 2001

Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates
Tsu-Jae King and Jackson H. Ho
U.S. Patent 5,893,949. April 1999

Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates
Tsu-Jae King and Jackson H. Ho
U.S. Patent 5,707,744. January 1998

Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions
Tsu-Jae King and Michael G. Hack
U.S. Patent 5,401,982. March 1995

Low temperature germanium-silicon on insulator thin-film transistor
Krishna C. Saraswat and Tsu-Jae King
U.S. Patent 5,250,818. October 1993