Patents - Chenming Hu
Semiconductor device with raised segment
Hao Yu Chen, Yee Chia Yeo, Fu Liang Yang and Chenming Hu
U.S. Patent 7,423,323. September 2008
High performance semiconductor devices fabricated with strain-induced processes and method for making same
Chung Hu Ke, Wen Chin Lee, Yee Chia Yeo, Chih Hsin Ko and Chenming Hu
U.S. Patent 7,394,136. July 2008
SOI chip with recess-resistant buried insulator and method of manufacturing the same
Yee Chia Yeo and Chenming Hu
U.S. Patent 7,372,107. May 2008
Relaxed silicon germanium substrate with low defect density
Chun Chieh Lin, Yee Chia Yeo, Chien Chao Huang, Chao Hsiung Wang, Tien Chih Chang, Chenming Hu, Fu Liang Yang, Shih Chang Chen, Mong Song Liang and Liang Gi Yao
U.S. Patent 7,357,838. April 2008
Methods of forming semiconductor devices with high-k gate dielectric
Chun Chieh Lin, Wen chin Lee, Chenming Hu, Shang Chih Chen, Chih Hao Wang, Fu Liang Yang and Yee Chia Yeo
U.S. Patent 7,354,830. April 2008
Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer
Yee Chia Yeo and Chenming Hu
U.S. Patent 7,354,843. April 2008
Strained silicon MOS devices
Chien Chao Huang, Chung Hu Ge, Wen Chin Lee, Chenming Hu, Carlos H. Diaz and Fu Liang Yang
U.S. Patent 7,342,289. March 2008
Transistor with a strained region and method of manufacture
Chun Chieh Lin, Wen Chin Lee, Yee Chia Yeo and Chenming Hu
U.S. Patent 7,335,929. February 2008
Semiconductor-on-insulator chip with<100>-oriented transistors
Fu Liang Yang, Yee Chia Yeo, Hung Wei Chen, Tim Tsao and Chenming Hu
U.S. Patent 7,319,258. January 2008
Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance
Chien Chao Huang, Yee Chia Yeo, Kuo Nan Yang, Chun Chieh Lin and Chenming Hu
U.S. Patent 7,312,136. December 2007
Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
Yee Chia Yeo, Fu Liang Yang and Chenming Hu
U.S. Patent 7,301,206. November 2007
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
Chao Yuan Su, Pei Haw Tsao, Hsin Hui Lee, Chender Huang, Shang Y. Hou, Shin Puu Jing, Hao Yi Tsai and Chenming Hu
U.S. Patent 7,294,937. November 2007
Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof
Chih Hao Wang, Ching Wei Tsai and Chenming Hu
U.S. Patent 7,279,756. October 2007
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
Yee Chia Yeo, How Yu Chen, Chien Chao Huang, Wen Chin Lee, Fu Liang Yang and Chenming Hu
U.S. Patent 7,268,024. September 2007
Interconnect with composite layers and method for fabricating the same
Chen Hua Yu, Horng Huei Tseng, Syun Ming Jang and Chenming Hu
U.S. Patent 7,265,447. September 2007
Contacts to semiconductor fin devices
Yee Chia Yeo, Fu Liang Yang and Chenming Hu
U.S. Patent 7,262,086. August 2007
Method for fabricating a body contact in a FinFET structure and a device including the same
Kuo Nan Yang, Yi Lang Chen, Hou Yu Chen, Fu Liang Yang and Chenming Hu
U.S. Patent 7,244,640. July 2007
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
Yee Chia Yeo, Chun Chieh Lin, Fu Liang Yang, Mong song Liang and Chenming Hu
U.S. Patent 7,238,989. July 2007
CMOS inverters configured using multiple-gate transistors
Yee Chia Yeo, Fu Liang Yang and Chenming Hu
U.S. Patent 7,214,991. May 2007
Strained silicon structure
Chung Hu Ge, Wen Chin Lee and Chenming Hu
U.S. Patent 7,208,754. April 2007
CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof
Hung Wei Chen, Ping Kun Wu, Chao Hsiung Wang, Fu Liang Yang and Chenming Hu
U.S. Patent 7,208,815. April 2007
Cobalt silicidation process for substrates with a silicon--germanium layer
Chien Chao Huang, Yee Chia Yeo, Chao Hsiung Wang, Chun Chieh Lin and Chenming Hu
U.S. Patent 7,202,122. April 2007
High performance tunneling-biased MOSFET and a process for its manufacture
Kuo-Nan Yang, Yi-Ling Chang, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,187,000. March 2007
Method for dicing semiconductor wafers
Hsin-Hui Lee, Chien-Chao Huang, Chao-Hsiung Wang, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,183,137. February 2007
Heterostructure resistor and method of forming the same
Yee-Chia Yeo, Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin and Chenming Hu
U.S. Patent 7,183,593. February 2007
Methods and structures for planar and multiple-gate transistors formed on SOI
Fu-Liang Yang, Yee-Chia Yeo and Chenming Hu
U.S. Patent 7,180,134. February 2007
Gate electrode for a semiconductor fin device
Yee-Chia Yeo, Hao-Yu Chen, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,176,092. February 2007
Self-aligned contact for silicon-on-insulator devices
Fu-Liang Yang, Yee-Chia Yeo, Horng-Huei Tseng and Chenming Hu
U.S. Patent 7,173,305. February 2007
Multiple-gate transistors formed on bulk substrates
Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,172,943. February 2007
Hybrid fractional-bit systems
Chenming Hu and Guobiao Zhang
U.S. Patent 7,167,109. January 2007
Strained silicon-on-insulator transistors with mesa isolation
Yee-Chia Yeo and Chenming Hu
U.S. Patent 7,157,774. January 2007
Silicon-on-insulator ULSI devices with multiple silicon film thicknesses
Fu-Liang Yang, Hao-Yu Chen, Yee-Chia Yeo, Carlos H. Diaz and Chenming Hu
U.S. Patent 7,141,459. November 2006
Dual work function CMOS gate technology based on metal interdiffusion
Igor Polishchuk, Pushkar Ranade, Tsu-Jae King and Chenming Hu
U.S. Patent 7,141,858. November 2006
Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling
Chao-Yuan Su, Pei-Haw Tsai, Hsin-Hui Lee, Chender Huang, Shang Y. Hou, Shin Puu Jeng, Hao-Yi Tsai and Chenming Hu
U.S. Patent 7,126,225. October 2006
Method of fabricating a necked FINFET device
Haur-Ywh Chen, Fang-Cheng Chen, Yi-Ling Chan, Kuo-Nan Yang, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,122,412. October 2006
Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chun-Chieh Lin and Chenming Hu
U.S. Patent 7,112,495. September 2006
Method for forming a device having multiple silicide types
Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin and Chenming Hu
U.S. Patent 7,112,483. September 2006
Copper wiring with high temperature superconductor (HTS) layer
Chen-Hua Yu, Horng-Huei Tseng, Chenming Hu and Chao-Hsiung Wang
U.S. Patent 7,105,928. September 2006
Contacts to semiconductor fin devices
Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,105,894. September 2006
Strained channel complementary field-effect transistors and methods of manufacture
Chih-Hsin Ko, Yee-Chia Yeo, Chun-Chieh Lin and Chenming Hu
U.S. Patent 7,101,742. September 2006
Thermal anneal process for strained-Si devices
Chung-Hu Ke, Wen-Chin Lee and Chenming Hu
U.S. Patent 7,098,119. August 2006
Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
Min-Hwa Chi, Yee-Chia Yeo and Chenming Hu
U.S. Patent 7,081,395. July 2006
Doping of semiconductor fin devices
Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang and Chenming Hu
U.S. Patent 7,074,656. July 2006
Resistor with reduced leakage
Yee-Chia Yeo and Chenming Hu
U.S. Patent 7,071,052. July 2006
Method for forming devices with multiple spacer widths
Howard Chih Hao Wang, Chenming Hu and Chun-Chieh Lin
U.S. Patent 7,057,237. June 2006
Strained channel transistor and methods of manufacture
Yee-Chia Yeo, Chih-Hsin Ko, Wen-Chin Lee and Chenming Hu
U.S. Patent 7,052,964. May 2006
Semiconductor structure having a strained region and a method of fabricating same
Wen-Chin Lee, Chung-Hu Ge and Chenming Hu
U.S. Patent 7,045,836. May 2006
Semiconductor device with high-k gate dielectric
Chun-Chieh Lin, Wen-Chin Lee, Chenming Hu, Shang-Chih Chen, Chih-Hao Wang, Fu-Liang Yang and Ye-Chia Yeng
U.S. Patent 7,045,847. May 2006
Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric
Yee-Chia Yeo and Chenming Hu
U.S. Patent 7,037,772. May 2006
Strained channel on insulator device
Chung-Hu Ge, Chao-Hsiung Wang, Chien-Chao Huang, Wen-Chin Lee and Chenming Hu
U.S. Patent 7,029,994. April 2006
CMOS device
Chien-Chao Huang, Chao-Hsiung Wang, Chung-Hu Ge and Chenming Hu
U.S. Patent 7,022,561. April 2006
SOI chip with mesa isolation and recess resistant regions
Yee-Chia Yeo, Hao-Yu Chen, Hsun-Chih Tsao, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,979,867. December 2005
Interconnect with composite barrier layers and method for fabricating the same
Chen-Hua Yu, Horng-Huei Tseng, Syun-Ming Jang and Chenming Hu
U.S. Patent 6,958,291. October 2005
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Mong-Song Liang and Chenming Hu
U.S. Patent 6,955,952. October 2005
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,953,972. October 2005
Suppression of MOSFET gate leakage current
Chenming Hu and Yee-Chia Yeo
U.S. Patent 6,949,769. September 2005
SOI chip with recess-resistant buried insulator and method of manufacturing the same
Yee-Chia Yeo and Chenming Hu
U.S. Patent 6,949,451. September 2005
High performance semiconductor devices fabricated with strain-induced processes and methods for making same
Chung-Hu Ke, Wen-Chin Lee, Yee-Chia Yeo, Chih-Hsin Ko and Chenming Hu
U.S. Patent 6,949,443. September 2005
Capacitor with enhanced performance and method of manufacture
Yee-Chia Yeo and Chenming Hu
U.S. Patent 6,940,705. September 2005
Capacitor that includes high permittivity capacitor dielectric
Yee-Chia Yeo and Chenming Hu
U.S. Patent 6,936,881. August 2005
Strained silicon layer semiconductor product employing strained insulator layer
Chien-Chao Huang, Chao-Hsiung Wang, Chung-Hu Ge, Wen-chin Lee and Chenming Hu
U.S. Patent 6,924,181. August 2005
Strained-channel transistor structure with lattice-mismatched zone
Yee-Chia Yeo, Chun-Chieh Lin, Wen-Chin Lee and Chenming Hu
U.S. Patent 6,921,913. July 2005
Semiconductor chip with gate dielectrics for high-performance and low-leakage applications
Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,906,398. June 2005
Strained silicon structure
Chung-Hu Ge, Wen-Chin Lee and Chenming Hu
U.S. Patent 6,902,965. June 2005
Strained channel on insulator device
Chung-Hu Ge, Chao-Hsiung Wang, Chien-Chao Huang, Wen-Chin Lee and Chenming Hu
U.S. Patent 6,900,502. May 2005
Strained-channel transistor and methods of manufacture
Yee-Chia Yeo, Chih-Hsin Ko, Wen-Chin Lee and Chenming Hu
U.S. Patent 6,882,025. April 2005
Relaxed silicon germanium substrate with low defect density
Chun-Chieh Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang, Chenming Hu, Fu-Liang Yang, Shih-Chang Chen, Mong-Song Liang and Liang-Gi Yao
U.S. Patent 6,878,610. April 2005
Semiconductor device with raised segment
Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,872,606. March 2005
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
Yee-Chia Yeo, Hao-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,867,433. March 2005
SOI chip with mesa isolation and recess resistant regions
Yee-Chia Yeo, Hao-Yu Chen, Hsun-Chih Tsao, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,864,149. March 2005
CMOS SRAM cell configured using multiple-gate transistors
Yee-Chia Yeo, Chenming Hu and Fu-Liang Yang
U.S. Patent 6,864,519. March 2005
Strained-channel multiple-gate transistor
Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,855,990. February 2005
Semiconductor nano-rod devices
Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,855,606. February 2005
Multiple-thickness gate oxide formed by oxygen implantation
Ya-Chin King, Tsu-Jae King and Chenming Hu
U.S. Patent 6,855,994. February 2005
Non-floating body device with enhanced performance
Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu and Da-Chi Lin
U.S. Patent 6,847,098. January 2005
Multiple-gate transistors with improved gate control
Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,844,238. January 2005
Suppression of MOSFET gate leakage current
Chenming Hu and Yee-Chia Yeo
U.S. Patent 6,830,953. December 2004
Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance
Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chun-Chieh Lin and Chenming Hu
U.S. Patent 6,812,116. November 2004
Low-voltage punch-through transient suppressor employing a dual-base structure
Bin Yu, Chenming Hu, Ya-Chin King, Jeffrey T. Pohlman and Rita Trivedi
U.S. Patent RE38,608. October 2004
Dual work function CMOS gate technology based on metal interdiffusion
Igor Polishchuk, Pushkar Ranade, Tsu-Jae King and Chenming Hu
U.S. Patent 6,794,234. September 2004
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
Haur-Ywh Chen, Yi-Ling Chan, Kuo-Nan Yang, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,784,071. August 2004
Multiple-thickness gate oxide formed by oxygen implantation
Ya-Chin King, Tsu-Jae King and Chenming Hu
U.S. Patent 6,753,229. June 2004
Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,720,619. April 2004
Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,703,271. March 2004
High performance PD SOI tunneling-biased MOSFET
Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,674,130. January 2004
Method of fabricating a non-floating body device with enhanced performance
Horng-Huei Tseng, Jyh-Chyurn Guo, Chenming Hu and Da-Chi Lin
U.S. Patent 6,627,515. September 2003
Antifuse structure suitable for VLSI application
Guobiao Zhang, Chenming Hu and Steve S. Chiang
U.S. Patent 6,603,187. August 2003
High performance PD SOI tunneling-biased MOSFET
Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,518,105. February 2003
Method of forming a transistor with a strained channel
Yee-Chia Yeo, Fu-Liang Yang and Chenming Hu
U.S. Patent 6,492,216. December 2002
FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu, Tsu-Jae King, Vivek Subramanian, Leland Chang, Xuejue Huang, Yang-Kyu Choi, Jakub Tadeusz Kedzierski, Nick Lindert, Jeffrey Bokor and Wen-Chin Lee
U.S. Patent 6,413,802. July 2002
Method of separating films from bulk substrates by plasma immersion ion implantation
Nathan W. Cheung, Xiang Lu and Chenming Hu
U.S. Patent 6,344,404. February 2002
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
Chenming Hu, Mansun John Chan, Hsing-Jen Wann and Ping Keung Ko
U.S. Patent 6,300,649. October 2001
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
Chenming Hu, Mansun John Chan, Hsing-Jen Wann and Ping Keung Ko
U.S. Patent 6,121,077. September 2000
Antifuse structure suitable for VLSI application
Guobiao Zhang, Chenming Hu and Steve S. Chiang
U.S. Patent 6,111,302. August 2000
Method of separating films from bulk substrates by plasma immersion ion implantation
Nathan W. Cheung, Xiang Lu and Chenming Hu
U.S. Patent 6,027,988. February 2000
Low-voltage punch-through transient suppressor employing a dual-base structure
Bin Yu, Chenming Hu, Ya-Chin King, Jeffrey T. Pohlman and Rita Trivedi
U.S. Patent 6,015,999. January 2000
Detection of process-induced damage on transistors in real time
Nguyen D. Bui, Chenming Hu, Donggun Park and Scott Zheng
U.S. Patent 6,005,409. December 1999
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
Chenming Hu, Mansun John Chan, Hsing-Jen Wann and Ping Keung Ko
U.S. Patent 5,982,003. November 1999
Low-voltage punch-through transient suppressor employing a dual-base structure
Bin Yu, Chenming Hu, Ya-Chin King, Jeffrey T. Pohlman and Rita Trivedi
U.S. Patent 5,880,511. March 1999
Realistic worst-case circuit simulation system and method
James Chieh-Tsung Chen, Zhihong Liu, Chenming Hu and Ping Keung Ko
U.S. Patent 5,790,436. August 1998
Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation
Chenming Hu and Hsing-Jen Wann
U.S. Patent 5,780,899. July 1998
Ferroelectric nonvolatile dynamic random access memory device
Chenming Hu and Reza Moazzami
U.S. Patent 5,768,182. June 1998
Electrically programmable antifuse
Abdul Rahim Forouhi, Esmat Z. Hamdy, Chenming Hu and John L. McCollum
U.S. Patent 5,670,818. September 1997
ESD and hot carrier resistant integrated circuit structure
Yi-Hen Wei, Ying T. Loh, Chung S. Wang and Chenming Hu
U.S. Patent 5,631,485. May 1997
Method of fabricating a self-aligned high speed MOSFET device
Chenming Hu and Hsing-Jen Wann
U.S. Patent 5,599,728. February 1997
Dynamic threshold voltage MOSFET having gate to body connection for ultra-low voltage operation
Chenming Hu, Ping K. Ko, Fariborz Assaderaghi and Stephen Parke
U.S. Patent 5,559,368. September 1996
Pseudo-nonvolatile memory incorporating data refresh operation
Chenming Hu and Fu-Chieh Hsu
U.S. Patent 5,511,020. April 1996
Method of forming an ESD and hot carrier resistant integrated circuit structure
Yi-Hen Wei, Ying T. Loh, Chung S. Wang and Chenming Hu
U.S. Patent 5,496,751. March 1996
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
Chenming Hu, Mansun J. Chan, Hsing-Jen Wann and Ping K. Ko
U.S. Patent 5,489,792. February 1996
Antifuse structure suitable for VLSI application
Guobiao Zhang, Chenming Hu and Steve S. Chiang
U.S. Patent 5,485,031. January 1996
Capacitorless DRAM device on silicon-on-insulator substrate
Chenming Hu and Hsing-Jen Wann
U.S. Patent 5,448,513. September 1995
Electrically programmable antifuse having a metal to metal structure
Abdul R. Forouhi, Esmat Z. Hamdy, Chenming Hu and John L. McCollum
U.S. Patent 5,387,812. February 1995
Electrically programmable antifuse and fabrication processes
Abdul R. Forouhi, Esmat Z. Hamdy, Chenming Hu and John L. McCollum
U.S. Patent 5,272,101. December 1993
Low voltage programming antifuse and transistor breakdown method for making same
Abdelshafy A. Eltoukhy, Gregory W. Bakker and Chenming Hu
U.S. Patent 5,163,180. November 1992
High voltage power IC process
Chenming Hu and Steven P. Sapp
U.S. Patent 4,908,328. March 1990
Electrically programmable memory device employing source side injection
Albert T. Wu, Ping K. Ko, Tung-Yi Chan and Chenming Hu
U.S. Patent 4,794,565. December 1988
Nonvolatile memory cell
Samuel T. Wang, Chenming Hu and Ying Shum
U.S. Patent 4,538,246. August 1985
Electrically erasable programmable read only memory
Chenming Hu
U.S. Patent 4,366,555. December 1982