Electrical Engineering and Computer Sciences

Electrical Engineering and Computer Sciences

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Faculty Publications - Alberto L. Sangiovanni-Vincentelli

Books

  • A. Mehrotra and A. L. Sangiovanni-Vincentelli, Noise Analysis of Radio Frequency Circuits, Boston: Kluwer Academic, 2004.
  • H. Hsieh, F. Balarin, and A. L. Sangiovanni-Vincentelli, Synchronous Equivalence: Formal Methods for Embedded Systems, Boston: Kluwer Academic Publishers, 2001.
  • S. P. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Cross-Talk Noise Immune VLSI Design using Regular Layout Fabrics, Boston: Kluwer Academic, 2001.
  • E. Charbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, and A. L. Sangiovanni-Vincentelli, Substrate Noise: Analysis and Optimization for IC Design, Boston: Kluwer Academic Publishers, 2001.
  • B. Tabbara, A. Tabbara, and A. L. Sangiovanni-Vincentelli, Function/Architecture Optimization and Co-Design of Embedded Systems, Kluwer International Series in Engineering and ComputerScience; SECS 585, Boston: Kluwer Academic Publishers, 2000.
  • A. Demir and A. L. Sangiovanni-Vincentelli, Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems, Kluwer International Series in Engineering and Computer Science; v. 425, Boston: Kluwer Academic, 1998.
  • F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. L. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, The Kluwer International Series in Engineering and Computer Science; SECS 404., Boston: Kluwer Academic Publishers, 1997.
  • T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Functional Optimization, Boston, MA: Kluwer Academic Publishers, 1997.
  • T. Villa, T. Kam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Logic Optimization, Boston: Kluwer Academic, 1997.
  • H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. L. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, Boston: Kluwer Academic, 1997.
  • F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. L. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, The Kluwer International Series In Engineering And Computer Science, Vol. 404, Boston, MA: Kluwer Academic Publishers, 1997.
  • H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. L. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, Boston, MA: Kluwer Academic Publishers, 1997.
  • R. Murgai, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Logic Synthesis for Field-Programmable Gate Arrays, The Kluwer International Series in Engineering and Computer Science; SECS 324, Boston: Kluwer Academic Publishers, 1995.
  • L. Lavagno and A. L. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, The Kluwer International Series in Engineering and Computer Science; SECS 0232., Boston: Kluwer Academic, 1993.
  • K. S. Kundert, J. K. White, and A. L. Sangiovanni-Vincentelli, Steady-State Methods for Simulating Analog and Microwave Circuits, The Kluwer International Series in Engineering and Computer Science; SECS94. VLSI, Computer Architecture and Digital Signal Processing, Boston: Kluwer Academic Publishers, 1990.
  • K. S. Kundert, J. K. White, and A. L. Sangiovanni-Vincentelli, Steady-State Methods for Simulating Analog and Microwave Circuits, Kluwer International Series in Engineering and Computer Science, Vol. 94, Boston, MA: Kluwer Academic Publishers, 1990.
  • J. K. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits, The Kluwer International Series in Engineering and Computer Science; SECS 20, Boston: Kluwer Academic Publishers, 1987.
  • G. De Micheli, A. L. Sangiovanni-Vincentelli, and P. Antognetti, Eds., Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, NATO Advanced Science Institute series. Series E, Applied Sciences, Vol. 136, Dordrecht, The Netherlands: Martinus Nijhoff Publishers, 1987.
  • A. L. Sangiovanni-Vincentelli, Ed., Selected Papers on Computer-Aided Design of Very Large Scale Integrated Circuits, Advances in Circuits and Systems, New York: IEEE Press, 1987.
  • J. K. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits, Kluwer International Series in Engineering and Computer Science, Vol. 20, Boston, MA: Kluwer Academic Publishers, 1986.
  • A. L. Sangiovanni-Vincentelli, Ed., Computer-Aided Design of VLSI Circuits and Systems, Advances in Computer-Aided Engineering Design, Vol. 1, Greenwich, CN: JAI Press, 1985.
  • R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, The Kluwer International Series in Engineering and Computer Science, Vol. 2, Boston, MA: Kluwer Academic Publishers, 1984.

Book chapters or sections

  • L. Carloni, F. De Bernardinis, C. Pinello, A. L. Sangiovanni-Vincentelli, and M. Sgroi, "Platform-based design for embedded systems," in The Embedded Systems Handbook, R. Zurawski, Ed., Boca Raton, FL: CRC Press, 2005, pp. 1-26.
  • A. Benveniste, B. Caillaud, L. P. Carloni, P. Caspi, and A. L. Sangiovanni-Vincentelli, "Causality and scheduling constraints in heterogeneous reactive systems modeling," in Formal Methods for Components and Objects: Proc. 2nd Intl. Symp. (FMCO 2003), F. S. de Boer, M. M. Bonsangue, S. Graf, and W. P. de Roever, Eds., Lecture Notes in Computer Science, Vol. 3188, Berlin: Springer-Verlag, 2004, pp. 1-16.
  • R. Ghosh and C. Tomlin, "Lateral inhibition through Delta-Notch signaling: A piecewise affine hybrid model," in Hybrid Systems: Computation and Control. Proc. 4th Intl. Workshop (HSCC 2001), M. D. Di Benedetto and A. L. Sangiovanni-Vincentelli, Eds., Lecture Notes in Computer Science, Vol. 2034, Berlin, Germany: Springer-Verlag, 2001, pp. 232-246.
  • S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "The relationship between logic synthesis and test," in Very Large Scale Integration: Proc. IFIP TC10/WG10.5 Intl. Conf. on Very Large Scale Integration (VLSI '89), G. Musgrave and U. Lauther, Eds., Amsterdam, Netherlands: North-Holland, 1990, pp. 175-186.
  • A. R. Newton, "Symbolic layout and procedural design," in Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. L. Sangiovanni-Vincentelli, and P. Antognetti, Eds., NATO Advanced Study Institute. Series E: Applied Sciences, Vol. 136, Dordrecht, Netherlands: Martinus Nijhoff Publishers, 1987, pp. 65-112.
  • G. De Micheli, M. Hofmann, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A design system for PLA-based digital circuits," in Advances in Computer-Aided Engineering Design, A. L. Sangiovanni-Vincentelli, Ed., Vol. 1, Greenwich, CT: JAI Press, 1985, pp. 285-264.

Articles in journals or magazines

Articles in conference proceedings

  • Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli, "SAT sweeping with local observability don't-cares," in Proc. 43rd ACM/IEEE Design Automation Conf., Piscataway, NJ: IEEE Press, 2006, pp. 229-234.
  • W. Zheng, J. Chong, C. Pinello, S. Kanajan, and A. L. Sangiovanni-Vincentelli, "Extensible and Scalable Time Triggered Scheduling," in Proceedings of the Fifth International Conference on Application of Concurrency to System Design, 2005.
  • J. van Greunen, D. Petrovic, A. Bonivento, J. M. Rabaey, K. Ramchandran, and A. L. Sangiovanni-Vincentelli, "Adaptive sleep discipline for energy conservation and robustness in dense sensor networks," in Proc. 2004 IEEE Intl. Conf. on Communications, Vol. 6, Piscataway, NJ: IEEE Press, 2004, pp. 3657-3662.
  • N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko, and A. L. Sangiovanni-Vincentelli, "Equisolvability of series vs. controller's topology in synchronous language equations," in Proc. 6th Design, Automation and Test in Europe Conf. and Exhibition (DATE 2003), N. Wehn and D. Verkest, Eds., Los Alamitos, CA: IEEE Computer Society, 2003, pp. 1154-1155.
  • M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform," in Proc. 10th Intl. Symp. on Hardware/Software Codesign (CODES 2002), New York, NY: ACM Press, 2002, pp. 151-156.
  • P. Buch, A. Narayan, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Logic synthesis for large pass transistor circuits," in 1997 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD 1997). Digest of Techical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1997, pp. 663-670.
  • R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa, "VIS: A system for verification and synthesis," in Lecture Notes in Computer Science: Computer Aided Verification, R. Alur and T. A. Henzinger, Eds., Vol. 1102, London, UK: Springer-Verlag, 1996, pp. 428-432.
  • E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. IEEE 1992 Intl. Conf. on Computer Design: VLSI in Computers and Processors, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 328-333.
  • A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Reduced offsets for two-level multi-valued logic minimization," in Proc. 275h ACM/IEEE Conf. on Design Automation (DAC '90), New York, NY: ACM, Inc., 1990, pp. 290-296.
  • A. Casotto, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Design management based on design traces," in Proc. 27th ACM/IEEE Conf. on Design Automation (DAC '90), New York, NY: ACM, Inc., 1990, pp. 136-141.
  • S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Irredundant sequential machines via optimal logic synthesis," in Proc. 23rd Annual Hawaii Intl. Conf. on System Sciences, Los Alamitos, CA: IEEE Computer Society Press, 1990, pp. 417-426.
  • A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A modified approach to two-level logic minimization," in 1988 IEEE Intl. Conf. on Computer-Aided Design (ICCAD-88). Digest of Technical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 106-109.
  • S. Devadas, A. R. Wang, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Boolean decomposition in multi-level logic optimization," in 1988 IEEE Intl. Conf. on Computer-Aided Design (ICCAD-88). Digest of Technical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 290-293.
  • S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Optimal logic synthesis and testability: Two faces of the same coin," in Proc. Intl. Test Conf. (ITC 1988), Washington, DC: IEEE Computer Society Press, 1988, pp. 4-12.
  • H. K. T. Ma, S. Devadas, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "An incomplete scan design approach to test generation for sequential machines," in Proc. Intl. Test Conf. (ITC 1988), Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 730-734.
  • S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Synthesis and optimization procedures for fully and easily testable sequential machines," in Proc. Intl. Test Conf. (ITC 1988), Los Alamitos, CA: IEEE Computer Society, 1988, pp. 621-630.
  • S. Devadas, A. R. Wang, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Boolean decomposition of programmable logic arrays," in Proc. 10th Annual IEEE Custom Integrated Circuits Conf. (CICC-88), New York, NY: IEEE, 1988, pp. 2.5/1-5.
  • H. K. T. Ma, S. Devadas, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Test generation for sequential finite state machines," in IEEE Intl. Conf. on Computer-Aided Design (ICCAD-87). Digest of Technical Papers, Washington, DC: IEEE Computer Society Press, 1987, pp. 288-291.
  • S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "MUSTANG: State assignment of finite state machines for optimal multi-level logic implementations," in Proc. IEEE Intl. Conf. on Computer-Aided Design (ICCAD-87). Digest of Technical Papers, Washington, DC: IEEE Computer Society Press, 1987, pp. 16-19.
  • C. H. Séquin, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "The Berkeley Synthesis Project [VLSI]," in 1987 Symp. on VLSI Circuits. Digest of Technical Papers, Piscataway, NJ: IEEE, 1987, pp. 1-4.
  • C. H. Séquin, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Highlights of VLSI research at Berkeley," in 1986 Proc. Fall Joint Computer Conf. (FJCC-86), H. S. Stone, Ed., Washington, DC: IEEE Computer Society Press, 1986, pp. 894-898.
  • J. K. White, R. A. Saleh, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "Accelerating relaxation algorithm for circuit simulation using waveform Newton, iterative step size refinement, and parallel techniques," in IEEE Intl. Conf. on Computer-Aided Design (ICCAD-85). Digest of Technical Papers, Washington, DC: IEEE Computer Society Press, 1985, pp. 5-7.
  • G. D. Hachtel, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Techniques for Programmable Logic Array folding," in Proc. 19th ACM/IEEE Design Automation Conf. (ICCAD-82), New York, NY: IEEE, 1982, pp. 147-155.
  • S. A. Ellis, K. H. Keller, A. R. Newton, D. O. Pederson, A. L. Sangiovanni-Vincentelli, and C. H. Séquin, "A symbolic layout design system," in Proc. 1982 IEEE Symp. on Circuits and Systems (ISCAS-82), New York, NY: IEEE, 1982, pp. 670-676.
  • R. K. Brayton, G. D. Hachtel, L. A. Hemachandra, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A comparison of logic minimization strategies using ESPRESSO: An APL program package for partitioned logic minimalization," in Proc. 1982 IEEE Intl. Symp. on Circuits and Systems (ISCAS-82), New York, NY: IEEE, 1982, pp. 42-48.
  • G. D. Hachtel, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "Invited Paper: Some results in optimal PLA folding," in Proc. IEEE Intl. Conf. on Circuits and Computers (ICCC '80), Vol. 2, New York, NY: IEEE, 1980, pp. 1023-1027.
  • G. De Micheli, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "New algorithms for timing analysis of large circuits," in Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS-80), Vol. 2, New York, NY: IEEE, 1980, pp. 439-443.

Technical Reports

Patents