Faculty Publications - Alberto L. Sangiovanni-Vincentelli

Books

• L. P. Carloni, R. Passerone, A. Pinto, and A. L. Sangiovanni-Vincentelli, Languages and Tools for Hybrid Systems Design, S. Malik, Ed., Foundations and Trends in Electronic Design Automation, Vol. 1, Hanover, MA: Now Publishers, 2006.
• A. Mehrotra and A. L. Sangiovanni-Vincentelli, Noise Analysis of Radio Frequency Circuits, Boston: Kluwer Academic, 2004. [abstract]
• H. Hsieh, F. Balarin, and A. L. Sangiovanni-Vincentelli, Synchronous Equivalence: Formal Methods for Embedded Systems, Boston: Kluwer Academic Publishers, 2001. [abstract]
• S. P. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Cross-Talk Noise Immune VLSI Design using Regular Layout Fabrics, Boston: Kluwer Academic, 2001. [abstract]
• E. Charbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, and A. L. Sangiovanni-Vincentelli, Substrate Noise: Analysis and Optimization for IC Design, Boston: Kluwer Academic Publishers, 2001. [abstract]
• B. Tabbara, A. Tabbara, and A. L. Sangiovanni-Vincentelli, Function/Architecture Optimization and Co-Design of Embedded Systems, Kluwer International Series in Engineering and ComputerScience; SECS 585, Boston: Kluwer Academic Publishers, 2000. [abstract]
• A. Demir and A. L. Sangiovanni-Vincentelli, Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems, Kluwer International Series in Engineering and Computer Science; v. 425, Boston: Kluwer Academic, 1998. [abstract]
• F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. L. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, The Kluwer International Series in Engineering and Computer Science; SECS 404., Boston: Kluwer Academic Publishers, 1997. [abstract]
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Functional Optimization, Boston, MA: Kluwer Academic Publishers, 1997. [abstract]
• T. Villa, T. Kam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Logic Optimization, Boston: Kluwer Academic, 1997. [abstract]
• H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. L. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, Boston: Kluwer Academic, 1997. [abstract]
• F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. L. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, The Kluwer International Series In Engineering And Computer Science, Vol. 404, Boston, MA: Kluwer Academic Publishers, 1997. [abstract]
• H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. L. Sangiovanni-Vincentelli, and I. Vassiliou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, Boston, MA: Kluwer Academic Publishers, 1997. [abstract]
• R. Murgai, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Logic Synthesis for Field-Programmable Gate Arrays, The Kluwer International Series in Engineering and Computer Science; SECS 324, Boston: Kluwer Academic Publishers, 1995. [abstract]
• L. Lavagno and A. L. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, The Kluwer International Series in Engineering and Computer Science; SECS 0232., Boston: Kluwer Academic, 1993. [abstract]
• K. S. Kundert, J. K. White, and A. L. Sangiovanni-Vincentelli, Steady-State Methods for Simulating Analog and Microwave Circuits, The Kluwer International Series in Engineering and Computer Science; SECS94. VLSI, Computer Architecture and Digital Signal Processing, Boston: Kluwer Academic Publishers, 1990. [abstract]
• K. S. Kundert, J. K. White, and A. L. Sangiovanni-Vincentelli, Steady-State Methods for Simulating Analog and Microwave Circuits, Kluwer International Series in Engineering and Computer Science, Vol. 94, Boston, MA: Kluwer Academic Publishers, 1990. [abstract]
• J. K. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits, The Kluwer International Series in Engineering and Computer Science; SECS 20, Boston: Kluwer Academic Publishers, 1987. [abstract]
• G. De Micheli, A. L. Sangiovanni-Vincentelli, and P. Antognetti, Eds., Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, NATO Advanced Science Institute series. Series E, Applied Sciences, Vol. 136, Dordrecht, The Netherlands: Martinus Nijhoff Publishers, 1987. [abstract]
• A. L. Sangiovanni-Vincentelli, Ed., Selected Papers on Computer-Aided Design of Very Large Scale Integrated Circuits, Advances in Circuits and Systems, New York: IEEE Press, 1987. [abstract]
• J. K. White and A. L. Sangiovanni-Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits, Kluwer International Series in Engineering and Computer Science, Vol. 20, Boston, MA: Kluwer Academic Publishers, 1986. [abstract]
• A. L. Sangiovanni-Vincentelli, Ed., Computer-Aided Design of VLSI Circuits and Systems, Advances in Computer-Aided Engineering Design, Vol. 1, Greenwich, CN: JAI Press, 1985. [abstract]
• R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, The Kluwer International Series in Engineering and Computer Science, Vol. 2, Boston, MA: Kluwer Academic Publishers, 1984. [abstract]

Book chapters or sections

• L. Benvenuti, A. Ferrari, E. Mazzi, and A. L. Sangiovanni-Vincentelli, "Contract-based design for computation and verification of a closed-loop hybrid system," in Hybrid Systems: Computation and Control. Proc. 11th Intl. Workshop (HSCC 2008), M. Egerstedt and B. Mishra, Eds., Lecture Notes in Computer Science, Vol. 4981, Berlin, Germany: Springer-Verlag, 2008, pp. 58-71.
• A. D. Ames, A. L. Sangiovanni-Vincentelli, and S. S. Sastry, "Homogeneous semantics preserving deployments of heterogeneous networks of embedded systems," in Networked Embedded Sensing and Control: Workshop Proc. (NESC 2005), P. J. Antsaklis and P. Tabuada, Eds., Lecture Notes in Control and Information, Vol. 331, Berlin, Germany: Springer-Verlag, 2006, pp. 127-154.
• A. Pinto, L. P. Carloni, R. Passerone, and A. L. Sangiovanni-Vincentelli, "Interchange format for hybrid systems: abstract semantics," in Hybrid Systems: Computation and Control. Proc. 9th Intl. Workshop (HSCC 2006), J. Hespanha and A. Tiwari, Eds., Lecture Notes in Computer Science, Vol. 3927, Berlin, Gemany: Springer-Verlag, 2006, pp. 491-506.
• A. Balluchi, A. Bicchi, E. Mazzi, A. L. Sangiovanni-Vincentelli, and G. Serra, "Hybrid modelling and control of the common rail injection system," in Hybrid Systems: Computation and Control. Proc. 9th Intl. Workshop (HCSS 2006), J. Hespanha and A. Tiwari, Eds., Lecture Notes in Computer Science, Vol. 3927, Berlin, Germany: Springer-Verlag, 2006, pp. 79-92.
• L. Carloni, F. De Bernardinis, C. Pinello, A. L. Sangiovanni-Vincentelli, and M. Sgroi, "Platform-based design for embedded systems," in The Embedded Systems Handbook, R. Zurawski, Ed., Boca Raton, FL: CRC Press, 2005, pp. 1-26.
• A. Benveniste, B. Caillaud, L. P. Carloni, P. Caspi, and A. L. Sangiovanni-Vincentelli, "Causality and scheduling constraints in heterogeneous reactive systems modeling," in Formal Methods for Components and Objects: Proc. 2nd Intl. Symp. (FMCO 2003), F. S. de Boer, M. M. Bonsangue, S. Graf, and W. P. de Roever, Eds., Lecture Notes in Computer Science, Vol. 3188, Berlin: Springer-Verlag, 2004, pp. 1-16.
• T. J. Koo, J. Liebman, C. Ma, B. Horowitz, A. L. Sangiovanni-Vincentelli, and S. S. Sastry, "Platform-based embedded software design for multi-vehicle multi-modal systems," in Embedded Software: Proc. 2nd Intl. Conf. (EMSOFT 2002), A. L. Sangiovanni-Vincentelli and J. Sifakis, Eds., Lecture Notes in Computer Science, Vol. 2491, Berlin, Germany: Springer-Verlag, 2002, pp. 32-45.
• R. Ghosh and C. Tomlin, "Lateral inhibition through Delta-Notch signaling: A piecewise affine hybrid model," in Hybrid Systems: Computation and Control. Proc. 4th Intl. Workshop (HSCC 2001), M. D. Di Benedetto and A. L. Sangiovanni-Vincentelli, Eds., Lecture Notes in Computer Science, Vol. 2034, Berlin, Germany: Springer-Verlag, 2001, pp. 232-246.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "The relationship between logic synthesis and test," in Very Large Scale Integration: Proc. IFIP TC10/WG10.5 Intl. Conf. on Very Large Scale Integration (VLSI '89), G. Musgrave and U. Lauther, Eds., Amsterdam, Netherlands: North-Holland, 1990, pp. 175-186.
• A. R. Newton, "Symbolic layout and procedural design," in Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. L. Sangiovanni-Vincentelli, and P. Antognetti, Eds., NATO Advanced Study Institute. Series E: Applied Sciences, Vol. 136, Dordrecht, Netherlands: Martinus Nijhoff Publishers, 1987, pp. 65-112.
• G. De Micheli, M. Hofmann, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A design system for PLA-based digital circuits," in Advances in Computer-Aided Engineering Design, A. L. Sangiovanni-Vincentelli, Ed., Vol. 1, Greenwich, CT: JAI Press, 1985, pp. 285-264.

Articles in journals or magazines

• A. L. Sangiovanni-Vincentelli, "Is a unified methodology for system-level design possible?," IEEE Design & Test of Computers, vol. 25, no. 4, pp. 346-357, July 2008.
• L. Yuan, G. Qu, T. Villa, and A. L. Sangiovanni-Vincentelli, "An FSM reengineering approach to sequential circuit synthesis by state splitting," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1159-1164, June 2008.
• A. Speranzon, C. fischione, K. H. Johansson, and A. L. Sangiovanni-Vincentelli, "A distributed minimum variance estimator for sensor networks," IEEE J. Selected Areas in Communications, vol. 26, no. 4, pp. 609-621, May 2008.
• C. Pinello, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Fault-tolerant distributed deployment of embedded control software," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 906-919, May 2008.
• N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko, and A. L. Sangiovanni-Vincentelli, "Compositionally progressive solutions of synchronous FSM equations," Discrete Event Dynamic Systems, vol. 18, no. 1, pp. 51-89, March 2008.
• W. Gosti, T. Villa, A. Saldanha, and A. L. Sangiovanni-Vincentelli, "FSM encoding for BDD representations," Intl. J. Applied Mathematics and Computer Science, vol. 17, no. 1, pp. 113-128, 2007.
• L. Mangeruca, M. Baleani, A. Ferrari, and A. L. Sangiovanni-Vincentelli, "Uniprocessor scheduling under precedence constraints for embedded systems design," ACM Trans. Embedded Computing Systems, vol. 7, no. 1, pp. Art. 6, Dec. 2007.
• A. L. Sangiovanni-Vincentelli and M. Di Natale, "Embedded system design for automotive applications (Cover Feature)," Computer, vol. 40, no. 10, pp. 42-51, Oct. 2007.
• B. Otis, S. Gambini, R. Shah, D. Steingart, E. Quevy, J. M. Rabaey, A. L. Sangiovanni-Vincentelli, and P. Wright, "Modelling and simulation technqiues for integrated, low-power wireless sensor networks," IET Computers & Digital Techniques, vol. 1, no. 5, pp. 528-526, Sep. 2007.
• A. L. Sangiovanni-Vincentelli, "Remembering Richard," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1357-1366, Aug. 2007.
• R. Passerone, J. R. Burch, and A. L. Sangiovanni-Vincentelli, "Refinement preserving approximations for the design and verification of heterogeneous systems," Formal Methods in System Design, vol. 31, no. 1, pp. 1-33, Aug. 2007.
• A. Bonivento, C. Fischione, L. Necchi, F. Pianegiani, and A. L. Sangiovanni-Vincentelli, "System level design for clustered wireless sensor networks," IEEE Trans. Industrial Informatics, vol. 3, no. 3, pp. 202-214, Aug. 2007.
• L. Mangeruca, M. Baleani, A. Ferrari, and A. L. Sangiovanni-Vincentelli, "Semantics-preserving design of embedded control software from synchronous models," IEEE Trans. Software Engineering, vol. 33, no. 8, pp. 497-509, Aug. 2007.
• F. Koushanfar, A. Davare, D. T. Nguyen, A. L. Sangiovanni-Vincentelli, and M. Potkonjak, "Techniques for maintaining connectivity in wireless ad-hoc networks under engergy constraints," ACM Trans. Embedded Computing Systems, vol. 6, no. 3, pp. Art. 16, July 2007.
• L. Albertoni, A. Balluchi, A. Casavola, C. Gambelli, E. Mosca, and A. L. Sangiovanni-Vincentelli, "Idle speed control of port-injection engines via the polynomial equation approach," Intl. J. Robust and Nonlinear Control: Special Issue on Polynomial Design Methods, vol. 17, no. 8, pp. 720-731, May 2007.
• H. Zeng, A. Davare, A. L. Sangiovanni-Vincentelli, S. Sonalkar, S. Kanajan, and C. Pinello, "Design space exploration of automotive platforms in Metropolis," SAE Trans.: J. of Passenger Cars--Electronic and Electrical Systems, vol. 115, no. 2006-01-1465, pp. 844-856, March 2007.
• A. L. Sangiovanni-Vincentelli, "Quo vadis, SLD? Reasoning about the trends and challenges of system level design (Invited Paper)," Proc. IEEE, vol. 95, no. 3, pp. 467-506, March 2007.
• P. Nuzzo, F. De Bernardinis, and A. L. Sangiovanni-Vincentelli, "Platform-based mixed signal design: Optimizing a high-performance pipelined ADC," Analog Integrated Circuits and Signal Processing, vol. 49, no. 3, pp. 343-358, Dec. 2006.
• D. Densmore, A. L. Sangiovanni-Vincentelli, and R. Passerone, "A platform-based taxonomy for ESL design," IEEE Design & Test of Computers, vol. 23, no. 5, pp. 359-374, Sep. 2006.
• A. Bonivento, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Platform based design for wireless sensor networks," Mobile Networks and Applications, vol. 11, no. 4, pp. 469-485, Aug. 2006.
• C. Umans, T. Villa, and A. L. Sangiovanni-Vincentelli, "Complexity of two-level logic minimization," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1230-1246, July 2006.
• A. Pinto, A. Bonivento, A. L. Sangiovanni-Vincentelli, R. Passerone, and M. Sgroi, "System level design paradigms: Platform-based design and communication synthesis," ACM Trans. Design Automation of Electronic Systems, vol. 11, no. 3, pp. 537-563, July 2006.
• J. M. Rabaey, F. De Bernardinis, A. Niknejad, B. Nikolic, and A. L. Sangiovanni-Vincentelli, "Embedding mixed-signal design in systems-on-chip (Invited Paper)," Proc. IEEE, vol. 94, no. 6, pp. 1070-1088, June 2006.
• L. Carloni, R. Passerone, A. Pinto, and A. L. Sangiovanni-Vincentelli, "Languages and tools for hybrid systems design," Foundations and Trends in Electronic Design automations, vol. 1, no. 1/2, pp. 1-193, June 2006.
• A. L. Sangiovanni-Vincentelli and A. Balluchi, "Guest Editors' Editorial for Special Issue on Advanced Design Methodologies in Automotive Control," Intl. J. Control: Special Issue on Advanced Design Methodologies in Automotive Control, vol. 79, no. 5, pp. 373-374, May 2006.
• A. Balluchi, L. Benvenuti, and A. L. Sangiovanni-Vincentelli, "Hybrid systems in automotive electronics design," Intl. J. Control: Special Issue on Advanced Design Methodologies in Automotive Control, vol. 79, no. 5, pp. 375-394, May 2006.
• L. P. Carloni and A. L. Sangiovanni-Vincentelli, "A framework for modeling the distributed deployment of synchronous designs," Formal Methods in System Design, vol. 28, no. 2, pp. 93-110, March 2006.
• D. Densmore, A. L. Sangiovanni-Vincentelli, and A. Donlin, "Leveraging programmability in electronic system-level designs," Xcell J., vol. 56, pp. 29-31, Jan. 2006.
• A. L. Sangiovanni-Vincentelli and A. Pinto, "An overview of embedded system design education at Berkeley," ACM Trans. Embedded Computing Systems, vol. 4, no. 3, pp. 472-499, Aug. 2005.
• S. P. Khatri, S. Sinha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SPFD-based wire removal in standard-cell and network-of-PLA circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 1020-1030, July 2004.
• A. L. Sangiovanni-Vincentelli, "Electronic-system design in the automobile industry," IEEE Micro, vol. 23, no. 3, pp. 8-18, May 2003.
• F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. L. Sangiovanni-Vincentelli, "Metropolis: An integrated electronic system design environment," IEEE Computer, vol. 36, no. 4, pp. 45-52, April 2003.
• B. Horowitz, J. Liebman, C. Ma, T. J. Koo, A. L. Sangiovanni-Vincentelli, and S. S. Sastry, "Platform-based embedded software design and system integration for autonomous vehicles (Invited Paper)," Proc. IEEE, vol. 91, no. 1, pp. 198-211, Jan. 2003.
• A. L. Sangiovanni-Vincentelli and G. Martin, "Platform-based design and software design methodology for embedded systems," IEEE Design & Test of Computers, vol. 18, no. 6, pp. 23-33, Nov. 2001.
• L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Theory of latency-insensitive design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1059-1076, Sep. 2001.
• R. E. Bryant, K. T. Cheng, A. B. Kahng, K. Keutzer, W. Maly, A. R. Newton, L. Pileggi, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Limitations and challenges of computer aided design technology for CMOS VLSI (Invited Paper)," Proc. IEEE, vol. 89, no. 3, pp. 341-365, March 2001.
• K. Keutzer, S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
• K. Keutzer, S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Invited Paper: System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
• A. Balluchi, L. Benvenuti, M. D. Di Benedetto, C. Pinello, and A. L. Sangiovanni-Vincentelli, "Invited Paper: Automotive engine control and hybrid systems: Challenges and opportunities," Proc. IEEE: Special Issue on Hybrid Systems, vol. 88, no. 7, pp. 888-912, July 2000.
• F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. L. Sangiovanni-Vincentelli, E. M. Sentovich, and K. Suzuki, "Synthesis of software programs for embedded control applications," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 834-849, June 1999.
• E. A. Lee and A. L. Sangiovanni-Vincentelli, "A framework for comparing models of computation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1217-1229, Dec. 1998.
• S. Edwards, L. Lavagno, E. A. Lee, and A. L. Sangiovanni-Vincentelli, "Design of embedded systems: Formal models, validation, and synthesis," Proc. IEEE, vol. 85, no. 3, pp. 366-390, March 1997.
• L. Lavagno, K. Keutzer, and A. L. Sangiovanni-Vincentelli, "Synthesis of hazard-free asynchronous circuits with bounded wire delays," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 1, pp. 61-86, Jan. 1995.
• A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Two-level minimization of multivalued functions with large offsets," IEEE Trans. Computers, vol. 42, no. 11, pp. 1325-1342, Nov. 1993.
• A. L. Sangiovanni-Vincentelli, A. El Gamal, and J. Rose, "Synthesis methods for field programmable gate arrays," Proc. IEEE, vol. 81, no. 7, pp. 1057-1083, July 1993.
• P. M. Xiao, E. Charbon, A. L. Sangiovanni-Vincentelli, T. Van Duzer, and S. R. Whiteley, "INDEX: An inductance extractor for superconducting circuits," IEEE Trans. Applied Superconductivity, vol. 3, no. 1, pt. 4, pp. 2629-2632, March 1993.
• S. Malik, L. Lavagno, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Symbolic minimization of multilevel logic and the input encoding problem," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 7, pp. 825-843, July 1992.
• A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Reduced offsets for minimization of binary-valued functions," IEEE Trans. Computer-Aided Design, vol. 10, no. 4, pp. 413-426, April 1991.
• S. Malik, E. M. Sentovich, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Retiming and resynthesis: Optimizing sequential networks with combinational techniques," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 1, pp. 74-84, Jan. 1991.
• R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, "Invited Paper: Multilevel logic synthesis," Proc. IEEE, vol. 78, no. 2, pp. 264-300, Feb. 1990.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Irredundant sequential machines via optimal logic synthesis," IEEE Trans. Computer-Aided Design, vol. 9, no. 1, pp. 8-18, Jan. 1990.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A synthesis and optimization procedure for fully and easily testable sequential machines," IEEE Trans. Computer-Aided Design, vol. 8, no. 10, pp. 1100-1107, Oct. 1989.
• S. Devadas, A. R. Wang, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Boolean decomposition in multilevel logic optimization," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 399-408, April 1989.
• S. Devadas, H. K. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "MUSTANG: State assignment of finite-state machines targeting multilevel logic implementations," IEEE Trans. Computer-Aided Design, vol. 7, no. 12, pp. 1290-1300, Dec. 1988.
• H. K. T. Ma, S. Devadas, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Test generation for sequential circuits," IEEE Trans. Computer-Aided Design, vol. 7, no. 10, pp. 1081-1093, Oct. 1988.
• W. Nye, D. C. Riley, A. L. Sangiovanni-Vincentelli, and A. L. Tits, "DELIGHT.SPICE: An optimization-based system for the design of integrated circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-7, no. 4, pp. 501-519, April 1988.
• R. K. Brayton, R. Rudell, A. L. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A multiple-level logic optimization system," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-6, no. 6, pp. 1062-1081, Nov. 1987.
• R. L. Rudell and A. L. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-6, no. 5, pp. 727-750, Sep. 1987.
• A. R. Newton, A. L. Sangiovanni-Vincentelli, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Invited Paper: CAD tools for ASIC design," Proc. IEEE, vol. 75, no. 6, pp. 765-776, June 1987.
• K. S. Kundert and A. L. Sangiovanni-Vincentelli, "Simulation of nonlinear circuits in the frequency domain," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-5, no. 4, pp. 521-535, Oct. 1986.
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Computer-aided design for VLSI circuits," IEEE Computer, vol. 19, no. 4, pp. 38-60, April 1986.
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Relaxation-based electrical simulation," IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 4, pp. 308-331, Oct. 1984.
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Relaxation-based electrical simulation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-3, no. 4, pp. 308-331, Oct. 1984.
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Relaxation-based electrical simulation," SIAM J. Scientific and Statistical Computing, vol. 4, no. 3, pp. 485-524, Sep. 1983. [abstract]
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Relaxation-based electrical simulation," IEEE Trans. Electron Devices, vol. ED-30, no. 9, pp. 1184-1207, Sep. 1983.
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Relaxation-based electrical simulation," SIAM J. Scientific and Statistical Computing, vol. 4, no. 3, pp. 485-524, Sep. 1983.
• G. De Micheli, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Symmetric displacement algorithms for the timing analysis of large scale circuits," IEEE Trans. Computer-Aided Design, vol. CAD-2, no. 3, pp. 167-180, Aug. 1983.
• G. De Micheli and A. L. Sangiovanni-Vincentelli, "Multiple constrained folding of programmable logic arrays: Theory and applications," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, no. 3, pp. 151-167, July 1983.
• E. Lelarasmee, A. E. Ruehli, and A. L. Sangiovanni-Vincentelli, "The waveform relaxation method for time-domain analysis of large scale integrated circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, no. 3, pp. 131-145, July 1982.
• G. D. Hachtel, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "An algorithm for optimal PLA folding," IEEE Trans. Computer-Aided Design, vol. CAD-1, no. 2, pp. 63-77, April 1982.
• R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, "A survey of optimization techniques for integrated-circuit design (Invited Paper)," Proc. IEEE, vol. 69, no. 10, pp. 1334-1362, Oct. 1981.
• G. D. Hachtel and A. L. Sangiovanni-Vincentelli, "A survey of third-generation simulation techniques (Invited Paper)," Proc. IEEE, vol. 69, no. 10, pp. 1264-1280, Oct. 1981.
• A. R. Newton, D. O. Pederson, A. L. Sangiovanni-Vincentelli, and C. H. Séquin, "Design aids for VLSI: The Berkeley perspective (Invited Paper)," IEEE Trans. Circuits and Systems, vol. 28, no. 7, pp. 666-680, July 1981.

Articles in conference proceedings

• A. Pinto, M. D'Angelo, C. Fischione, E. Scholte, and A. L. Sangiovanni-Vincentelli, "Synthesis of embedded networks for building automation and control," in Proc. 2008 American Control Conf. (ACC '08), Dayton, OH: American Automatic Control Council, 2008, pp. 920-925.
• P. G. Park, C. Fischione, A. bonivento, K. H. Johansson, and A. L. Sangiovanni-Vincentelli, "Breath: A self-adapting protocol for wireless sensor networks in control and automation," in Proc. 5th Annual IEEE Communications Society Conf. on Sensor, Mesh and Ad Hoc Communications and Networks (SECON 2008), Piscataway, NJ: IEEE Press, 2008, pp. 323-331.
• Y. Li, C. Wu, A. L. Sangiovanni-Vincentelli, and J. M. Rabaey, "Design and optimization of an MB-OFDM ultra-wideband receiver front-end," in Proc. 4th IEEE Intl. Conf. on Circuits and Systems for Communications (ICCSC 2008), Piscataway, NJ: IEEE Press, 2008, pp. 502-506.
• A. Ghosal, A. L. Sangiovanni-Vincentelli, and S. Kanajan, "A study of monetary cost analysis for product-line architectures," in Proc. 2008 SAE World Congress & Exhibition (SAE '07), Warrendale, PA: SAE International, 2008.
• Y. Li, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Analysis of interference effects in MB-OFDM UWB systems," in Proc. 2008 IEEE Wireless Communications and Networking Conf. (WCNC '08), Piscataway, NJ: IEEE Press, 2008, pp. 165-170.
• T. Meyerowitz, A. L. Sangiovanni-Vincentelli, M. Sauermann, and D. Langen, "Source-level timing annotation and simulation for a heterogeneous multiprocessor," in Proc. 2008 Design, Automation and Test in Europe (DATE '08), Leuven, Belgium: European Design and Automation Association, 2008, pp. 276-279.
• K. Chatterjee, A. Ghosal, T. A. Henzinger, D. Iercan, C. M. Kirsch, C. Pinello, and A. L. Sangiovanni-Vincentelli, "Logical reliability of interacting real-time tasks," in Proc. 2008 Design, Automation and Test in Europe (DATE '08), Leuven, Belgium: European Design and Automation Associaton, 2008, pp. 909-914.
• R. Marculescu, B. Nikolic, and A. L. Sangiovanni-Vincentelli, ""Fresh air": The Emerging Landscape of Design for Networked Embedded Systems (Session Abstract)," in Proc. 5th IEEE/ACM Intl. Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 124-124.
• A. Benveniste, P. Caspi, M. di Natale, C. Pinello, A. L. Sangiovanni-Vincentelli, and S. Tripakis, "Loosely time-triggered architectures based on communication-by-sampling," in Proc. 7th IEEE/ACM Intl. Conf. on Embedded Software (EMSOFT 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 231-239.
• R. Ernst, G. Spiegelberg, T. Weber, H. Kopetz, A. L. Sangiovanni-Vincentelli, and M. Jersak, "Automotive Networks: Are New Busses and Gateways the Answer or Just Another Challenge? (Panel Session)," in Proc. 5th IEEE/ACM Intl. Conf. on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 263-263.
• A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "A communication synthesis infrastructure for heterogeneous networked control systems and its application to building automation and control," in Proc. 7th IEEE/ACM Intl. Conf. on Embedded Software (EMSOFT 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 21-29.
• N. Smith, A. Chien, C. Hegarty, W. C. Rhines, A. L. Sangiovanni-Vincentelli, and F. Winters, "Electronics: The New Differential in the Automotive Industry (Panel Discussion)," in Proc. 44th IEEE/ACM Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 446-446.
• A. Davare, Q. Zhu, M. Di Natale, C. Pinello, S. Kanajan, and A. L. Sangiovanni-Vincentelli, "Period optimization for hard real-time distributed automotive systems," in Proc. 44th ACM/IEEE Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 278-283.
• A. Ghosal, S. Kanajan, R. Urbance, and A. L. Sangiovanni-Vincentelli, "An initial study on monetary cost evaluation for the design of automotive electronic architectures," in Proc. 2007 SAE World Congress & Exhibition (SAE '07), Vol. 116, Warrendale, PA: SAE International, 2007, pp. 1273-1275.
• T. Villa, S. Zharikova, N. Yevtushenko, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A new algorithm for the largest compositionally progressive solution of synchronous language equations," in Proc. 17th ACM Great Lakes Symp. on VLSI (GLSVLSI 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 441-444.
• L. Necchi, A. Bonivento, L. Lavagno, A. L. Sangiovanni-Vincentelli, and L. Vanzago, "E2RINA: An energy efficient and reliable in-network aggregation for clustered wireless sensor networks," in Proc. 2007 IEEE Wireless Communications and Networking Conf. (WCNS '07), Piscataway, NJ: IEEE Press, 2007, pp. 3366-3371.
• A. Davare, D. Densmore, T. Meyerowitz, A. Pinto, A. L. Sangiovanni-Vincentelli, G. Yang, H. Zeng, and Q. Zhu, "A next-generation framework for platform-based design," in Proc. 2007 Design and Verification Conference (DVCon '07), 2007.
• C. Fischione, A. Bonivento, K. H. Johansson, and A. L. Sangiovanni-Vincentelli, "Cooperative diversity with disconnection constraints and sleep discipline for power control in wireless sensor networks," in Proc. 63rd IEEE Vehicular Technology Conf. (VTC 2006-Spring), Piscataway, NJ: IEEE Press, 2006, pp. 578-582.
• F. De Bernardinis, P. Nuzzo, and A. L. Sangiovanni-Vincentelli, "Robust system-level design with analog platforms," in Proc. 2006 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD '06), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 334-341.
• A. Fazzi, L. Magagni, M. De Dominicis, P. Zoffoli, R. Canegallo, R. L. Rolandi, A. L. Sangiovanni-Vincentelli, and R. Guerrieri, "Yield prediction for 3D capacitive interconnections," in Proc. 2006 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD '06), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 809-814.
• G. Yang, H. Hsieh, X. Chen, F. Balarin, and A. L. Sangiovanni-Vincentelli, "Constraints assisted modeling and validation in Metropolis framework," in 40th Asilomar Conf. on Signals, Systems and Computers (ACSSC 2006) Conference Record, M. B. Matthews, Ed., Piscataway, NJ: IEEE Press, 2006, pp. 1469-1474.
• A. Benveniste, B. Caillaud, L. P. Carloni, P. Caspi, A. L. Sangiovanni-Vincentelli, and S. Tripakis, "Communication by sampling in time-sensitive distributed systems," in Proc. 6th IEEE/ACM Intl. Conf. on Embedded Software (EMSOFT 2006), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 152-160.
• A. Ghosal, A. L. Sangiovanni-Vincentelli, C. M. Kirsch, T. A. Henzinger, and D. Iercan, "A hierarchical coordination language for interacting real-time tasks," in Proc. 6th IEEE/ACM Intl. Conf. on Embedded Systems (EMSOFT 2006), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 132-141.
• M. L. McKelvin Jr., C. Pinello, S. Kanajan, J. Wysocki, and A. L. Sangiovanni-Vincentelli, "Model-based design of heterogeneous systems for fault tree analysis," in Proc. 24th Intl. System Safety Conf. (ISSC 2006), Unionville, VA: System Safety Society, Inc., 2006, pp. 400-409.
• A. Balluchi, A. Casagrande, P. Collins, A. Ferrari, T. Villa, and A. L. Sangiovanni-Vincentelli, "Ariadne: A framework for reachability analysis of hybrid automata," in Proc. 17th Intl. Symp. on Mathematical Theory of Networks and Systems (MTNS 2006), 2006, pp. 1259-1267.
• Q. Zhu, A. Davare, and A. L. Sangiovanni-Vincentelli, "A semantic-driven synthesis flow for platform-based design," in Proc. 4th ACM/IEEE Intl. Conf. on Formal Methods and Models for Co-Design (MEMOCODE 2006), Piscataway, NJ: IEEE Press, 2006, pp. 199-199.
• Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli, "SAT sweeping with local observability don't-cares," in Proc. 43rd ACM/IEEE Design Automation Conf. (DAC 2006), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 229-234.
• C. Liu, A. Kondratyev, Y. Watanabe, J. Desel, and A. L. Sangiovanni-Vincentelli, "Schedulability analysis of Petri nets based on structural properties," in Proc. 6th Intl. Conf. on Application of Concurrency to System Design (ACSD 2006), K. Goossens and L. Petrucci, Eds., Los Alamitos, CA: IEEE Computer Society, 2006, pp. 69-78.
• S. Kakita, Y. Watanabe, D. Densmore, A. Davare, and A. L. Sangiovanni-Vincentelli, "Functional model exploration for multimedia applications via algebraic operators," in Proc. 6th Intl. Conf. on Application of Concurrency to System Design (ACSD 2006), K. Goossens and L. Petrucci, Eds., Los Alamitos, CA: IEEE Computer Society, 2006, pp. 229-238.
• A. Balluchi, L. Benvenuti, M. D. Di Benedetto, T. Villa, and A. L. Sangiovanni-Vincentelli, "Idle speed control -- A benchmark for hybrid system research (Invited Paper)," in Proc. 2nd IFAC Conf. on Analysis and Design of Hybrid Systems (ADHS 2006), C. G. Cassandras, A. Giua, C. Seatzu, and J. Zaytoon, Eds., Laxenburg, Austria: International Federation of Automnatic Control, 2006, pp. 2.
• L. Mangeruca, M. Baleani, A. Ferrari, and A. L. Sangiovanni-Vincentelli, "Uniprocessor scheduling under precedence constraints," in Proc. 12th IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS 2006), S. Goddard and J. S. Liu, Eds., Los Alamitos, CA: IEEE Computer Society, 2006, pp. 157-166.
• R. Marculescu, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Is "network" the next "big idea" in design?," in Proc. 2006 Design, Automation and Test in Europe (DATE '06), Leuven, Belgium: European Design and Automation Association, 2006, pp. 254-256.
• G. Yang, X. Chen, F. Balarin, H. Hsieh, and A. L. Sangiovanni-Vincentelli, "Communication and co-simulation infrastructure for heterogeneous system integration," in Proc. 2006 Design, Automation and Test in Europe (DATE '06), Leuven, Belgium: European Design and Automation Association, 2006, pp. 462-467.
• S. Kanajan, H. Zeng, C. Pinello, and A. L. Sangiovanni-Vincentelli, "Exploring trade-off's between centralized versus decentralized automotive architectures using a virtual integration environment," in Proc. 2006 Design, Automation and Test in Europe (DATE '06), Leuven, Belgium: European Design and Automation Association, 2006, pp. 548-553.
• D. Densmore, A. Donlin, and A. L. Sangiovanni-Vincentelli, "FPGA architecture characterization for system level performance analysis," in Proc. 2006 Design, Automation and Test in Europe (DATE '06), Leuven, Belgium: European Design and Automation Association, 2006, pp. 734-739.
• A. Bonivento, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Platform-based design of wireless sensor networks for industrial applications," in Proc. 2006 Design, Automation and Test in Europe (DATE '06), Leuven, Belgium: European Design and Automation Association, 2006, pp. 1103-1107.
• A. L. Sangiovanni-Vincentelli, "Automotive Electronics: Steady Growth for Years to Come! (Keynote Address)," in Proc. 11th Asia and South Pacific Design Automation Conf. (ASP-DAC 2006), Piscataway, NJ: IEEE Press, 2006, pp. vii-ix.
• A. Bonivento, C. Fischione, and A. L. Sangiovanni-Vincentelli, "Randomized protocol stack for ubiquitous networks in indoor environments," in Proc. 3rd IEEE Consumer Communications and Networking Conf. (CCNC 2006), Vol. 1, Piscataway, NJ: IEEE Press, 2006, pp. 152-156.
• C. Fischione, A. Bonivento, A. L. Sangiovanni-Vincentelli, F. Santucci, and K. H. Johansson, "Performance analysis of collaborative spatio-temporal processing for wireless sensor networks," in Proc. 3rd IEEE Consumer Communications and Networking Conf. (CCNC 2006), Vol. 1, Piscataway, NJ: IEEE Press, 2006, pp. 325-329.
• W. Zheng, J. Chong, C. Pinello, S. Kanajan, and A. L. Sangiovanni-Vincentelli, "Extensible and Scalable Time Triggered Scheduling," in Proceedings of the Fifth International Conference on Application of Concurrency to System Design, 2005. [abstract]
• J. van Greunen, D. Petrovic, A. Bonivento, J. M. Rabaey, K. Ramchandran, and A. L. Sangiovanni-Vincentelli, "Adaptive sleep discipline for energy conservation and robustness in dense sensor networks," in Proc. 2004 IEEE Intl. Conf. on Communications, Vol. 6, Piscataway, NJ: IEEE Press, 2004, pp. 3657-3662.
• N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko, and A. L. Sangiovanni-Vincentelli, "Equisolvability of series vs. controller's topology in synchronous language equations," in Proc. 6th Design, Automation and Test in Europe Conf. and Exhibition (DATE 2003), N. Wehn and D. Verkest, Eds., Los Alamitos, CA: IEEE Computer Society, 2003, pp. 1154-1155.
• M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "HW/SW Partitioning and Code Generation of Embedded Control Applica- tions on a Reconfigurable Architecture Platform," in Proceedings of the tenth international symposium on Hardware/software codesign, 2002.
• M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform," in Proc. 10th Intl. Symp. on Hardware/Software Codesign (CODES 2002), New York, NY: ACM Press, 2002, pp. 151-156.
• P. Buch, A. Narayan, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Logic synthesis for large pass transistor circuits," in 1997 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD 1997). Digest of Techical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1997, pp. 663-670.
• R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa, "VIS: A system for verification and synthesis," in Lecture Notes in Computer Science: Computer Aided Verification, R. Alur and T. A. Henzinger, Eds., Vol. 1102, London, UK: Springer-Verlag, 1996, pp. 428-432.
• E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. IEEE 1992 Intl. Conf. on Computer Design: VLSI in Computers and Processors, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 328-333.
• A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Reduced offsets for two-level multi-valued logic minimization," in Proc. 275h ACM/IEEE Conf. on Design Automation (DAC '90), New York, NY: ACM, Inc., 1990, pp. 290-296.
• A. Casotto, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Design management based on design traces," in Proc. 27th ACM/IEEE Conf. on Design Automation (DAC '90), New York, NY: ACM, Inc., 1990, pp. 136-141.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Irredundant sequential machines via optimal logic synthesis," in Proc. 23rd Annual Hawaii Intl. Conf. on System Sciences, Los Alamitos, CA: IEEE Computer Society Press, 1990, pp. 417-426.
• A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A modified approach to two-level logic minimization," in 1988 IEEE Intl. Conf. on Computer-Aided Design (ICCAD-88). Digest of Technical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 106-109.
• S. Devadas, A. R. Wang, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Boolean decomposition in multi-level logic optimization," in 1988 IEEE Intl. Conf. on Computer-Aided Design (ICCAD-88). Digest of Technical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 290-293.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Optimal logic synthesis and testability: Two faces of the same coin," in Proc. Intl. Test Conf. (ITC 1988), Washington, DC: IEEE Computer Society Press, 1988, pp. 4-12.
• H. K. T. Ma, S. Devadas, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "An incomplete scan design approach to test generation for sequential machines," in Proc. Intl. Test Conf. (ITC 1988), Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 730-734.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Synthesis and optimization procedures for fully and easily testable sequential machines," in Proc. Intl. Test Conf. (ITC 1988), Los Alamitos, CA: IEEE Computer Society, 1988, pp. 621-630.
• S. Devadas, A. R. Wang, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Boolean decomposition of programmable logic arrays," in Proc. 10th Annual IEEE Custom Integrated Circuits Conf. (CICC-88), New York, NY: IEEE, 1988, pp. 2.5/1-5.
• H. K. T. Ma, S. Devadas, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Test generation for sequential finite state machines," in IEEE Intl. Conf. on Computer-Aided Design (ICCAD-87). Digest of Technical Papers, Washington, DC: IEEE Computer Society Press, 1987, pp. 288-291.
• S. Devadas, H. K. T. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "MUSTANG: State assignment of finite state machines for optimal multi-level logic implementations," in Proc. IEEE Intl. Conf. on Computer-Aided Design (ICCAD-87). Digest of Technical Papers, Washington, DC: IEEE Computer Society Press, 1987, pp. 16-19.
• C. H. Séquin, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "The Berkeley Synthesis Project [VLSI]," in 1987 Symp. on VLSI Circuits. Digest of Technical Papers, Piscataway, NJ: IEEE, 1987, pp. 1-4. [abstract]
• C. H. Séquin, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Highlights of VLSI research at Berkeley," in 1986 Proc. Fall Joint Computer Conf. (FJCC-86), H. S. Stone, Ed., Washington, DC: IEEE Computer Society Press, 1986, pp. 894-898.
• J. K. White, R. A. Saleh, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "Accelerating relaxation algorithm for circuit simulation using waveform Newton, iterative step size refinement, and parallel techniques," in IEEE Intl. Conf. on Computer-Aided Design (ICCAD-85). Digest of Technical Papers, Washington, DC: IEEE Computer Society Press, 1985, pp. 5-7. [abstract]
• G. D. Hachtel, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Techniques for Programmable Logic Array folding," in Proc. 19th ACM/IEEE Design Automation Conf. (ICCAD-82), New York, NY: IEEE, 1982, pp. 147-155.
• S. A. Ellis, K. H. Keller, A. R. Newton, D. O. Pederson, A. L. Sangiovanni-Vincentelli, and C. H. Séquin, "A symbolic layout design system," in Proc. 1982 IEEE Symp. on Circuits and Systems (ISCAS-82), New York, NY: IEEE, 1982, pp. 670-676. [abstract]
• R. K. Brayton, G. D. Hachtel, L. A. Hemachandra, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A comparison of logic minimization strategies using ESPRESSO: An APL program package for partitioned logic minimalization," in Proc. 1982 IEEE Intl. Symp. on Circuits and Systems (ISCAS-82), New York, NY: IEEE, 1982, pp. 42-48. [abstract]
• G. D. Hachtel, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "Some results in optimal PLA folding (Invited Paper)," in Proc. IEEE Intl. Conf. on Circuits and Computers (ICCC '80), Vol. 2, New York, NY: IEEE, 1980, pp. 1023-1027. [abstract]
• G. De Micheli, A. L. Sangiovanni-Vincentelli, and A. R. Newton, "New algorithms for timing analysis of large circuits," in Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS-80), Vol. 2, New York, NY: IEEE, 1980, pp. 439-443. [abstract]

Technical Reports

• G. Wang, M. Di Natale, and A. L. Sangiovanni-Vincentelli, "Spatial and Temporal Cost Analysis on OSEK Implementations of Synchronous Reactive Semantics Preserving Communication Protocols," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-149, Dec. 2008. [abstract]
• A. Pinto, L. Carloni, and A. L. Sangiovanni-Vincentelli, "COSI: A Public-Domain Design Framework for the Design of Interconnection Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-22, March 2008. [abstract]
• A. Pinto, A. L. Sangiovanni-Vincentelli, and L. Carloni, "A Methodology and an Open Software Infrastructure for Constraint-Driven Synthesis of On-Chip Communications," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2007-130, Nov. 2007. [abstract]
• G. Wang, M. Di Natale, and A. L. Sangiovanni-Vincentelli, "An OSEK/VDX Implementation of Synchronous Reactive Semantics Preserving Communication Protococls," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2007-81, June 2007. [abstract]
• A. Davare, J. Chong, Q. Zhu, D. M. Densmore, and A. L. Sangiovanni-Vincentelli, "Classification, Customization, and Characterization: Using MILP for Task Allocation and Scheduling," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-166, Dec. 2006. [abstract]
• A. Pinto, L. Carloni, and A. L. Sangiovanni-Vincentelli, "Synthesis of On-Chip Interconnection Structures: From Point-To-Point Links to Networks-on-Chip," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-147, Nov. 2006. [abstract]
• A. Pinto, L. Carloni, and A. L. Sangiovanni-Vincentelli, "Synthesis of Low Power NOC Topologies under Bandwidth Constraints," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-137, Oct. 2006. [abstract]
• Q. Zhu, Z. Zhang, A. Pinto, and A. L. Sangiovanni-Vincentelli, "On-Chip Networks Modeling and Simulation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-126, Oct. 2006. [abstract]
• A. Ghosal, T. A. Henzinger, D. Iercan, C. Kirsch, and A. L. Sangiovanni-Vincentelli, "Hierarchical Timing Language," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-79, May 2006. [abstract]
• A. Davare, Q. Zhu, and A. L. Sangiovanni-Vincentelli, "A Platform-based Design Flow for Kahn Process Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-30, March 2006. [abstract]
• G. Wang, A. Mishchenko, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Synthesizing FSMs According to co-bu chi Properties," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M05/13, April 2005.
• D. Gasperini, A. Pinto, and A. L. Sangiovanni-Vincentelli, "METROC: A Metropolis Based Design Methodology Developed in a C++ Framework," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M05/6, Jan. 2005.
• C. Umans, T. Villa, and A. L. Sangiovanni-Vincentelli, "Complexity of Two-Level Minimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M04/45, 2004.
• J. R. Burch, R. Passerone, and A. L. Sangiovanni-Vincentelli, "Notes on Agent Algebras," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/38, 2003.
• A. Benveniste, L. P. Carloni, P. Caspi, and A. L. Sangiovanni-Vincentelli, "Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/23, 2003.
• N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko, and A. L. Sangiovanni-Vincentelli, "Sequential Synthesis by Language Equation solving," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/9, 2003.
• A. Balluchi, L. Benbenuti, T. Villa, H. Wong-Toi, and A. L. Sangiovanni-Vincentelli, "Maximal Controllers for Hybrid Systems with Multiple Time Event Separations," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/8, 2003.
• T. C. Meyerowitz and A. L. Sangiovanni-Vincentelli, "Describing, Simulating, and Optimizing Hierarchical Bus Scheduling Policies," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/5, 2003.
• L. P. Carloni and A. L. Sangiovanni-Vincentelli, "Seeking Equilibrium between Communication and Computation in System-level Design," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/24, May 2003.
• M. Sgroi, A. Kondratyev, Y. Watanabe, and A. L. Sangiovanni-Vincentelli, "Synthesis of Petri Nets from MSC-based Specifications," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M02/38, 2002.
• T. R. Shiple, R. K. Brayton, G. Berry, and A. L. Sangiovanni-Vincentelli, "Logical Analysis of Combinational Cycles," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M02/21, 2002.
• A. Nardi, L. Daniel, and A. L. Sangiovanni-Vincentelli, "A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M02/20, 2002.
• A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Constraint-driven Communications Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M02/12, 2002.
• W. Gosti, S. P. Khatri, and A. L. Sangiovanni-Vincentelli, "Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/66, 2000.
• M. Broucke, M. Di Benedetto, S. Di Gennard, and A. L. Sangiovanni-Vincentelli, "Optimal Control Using Bisimulations," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/34, 2000.
• B. Tabbara, A. Tabbara, and A. L. Sangiovanni-Vincentelli, "Hardware and Software Representation, Optimization, and Co-Synthesis for Embedded Systems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/7, 2000.
• L. Carloni and A. L. Sangiovanni-Vincentelli, "Recycle, Reuse, Reduce," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/53, 1999.
• S. Khatri, S. Sinha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/51, 1999.
• S. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A VLSI Design Methodology Using a Network of PLAs Embedded in a Regular Layout Fabric," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/50, 1999.
• B. Tabbara and A. L. Sangiovanni-Vincentelli, "Data Flow and Control for Hardware and Software Co-Synthesis in Embedded Systems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/31, 1999.
• S. Khatri, S. Sinha, A. Kuehlmann, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SPFD-Based Wire Removal in a Network of PLAs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/17, 1999.
• Y. Jiang, S. Khatri, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "A Multi-Layer Area Routing Methodology Using a Boolean Satisfiability Based Router," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/16, 1999.
• S. Khatri, R. K. Brayton, A. Mehrotra, A. L. Sangiovanni-Vincentelli, and M. Prasad, "Routing Techniques for Deep Sub-Micron Technologies," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/15, 1999.
• L. Carloni, K. McMillan, and A. L. Sangiovanni-Vincentelli, "Latency Insensitive Protocols," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/11, 1999.
• A. Mehrotra and A. L. Sangiovanni-Vincentelli, "Simulation Techniques for Noise in Non-Autonomous Radio Frequency Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/10, 1999.
• H. Hsieh, F. Balarin, and A. L. Sangiovanni-Vincentelli, "Synchronous Equivalence for Embedded Systems: A Tool for Design Exploration," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/1, 1999.
• S. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A Layout and Design Methodology for Deep Sub-micron Applications Using Networks of PLAs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/68, 1998.
• S. Khatri, S. Krishnan, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "Combinational Verification Revisted," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/60, 1998.
• S. Khatri, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "Accurate Automatic Timing Characterization of Static CMOS Libraries," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/58, 1998.
• B. Tabbara, E. Filippi, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "RTL Generation of Hardware Components of a Mixed Hardware/Software Implementation of Embedded Systems for System Level Co-Simulation in VHDL," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/55, 1998.
• B. Tabbara, E. Filippi, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Fast Hardware-Software Co-Simulation Using VHDL Models," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/54, 1998.
• S. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Multi-Valued Network Compaction Using Redundancy Removal," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/44, 1998.
• S. Tasiran, S. Khatri, S. Yovine, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Accurate Timing Analysis in the Presence of Cross-Talk Using Timed Automata," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/25, 1998.
• S. Khatri, A. Mehrotra, R. K. Brayton, R. Otten, and A. L. Sangiovanni-Vincentelli, "A Noise-Immune VLSI Layout Methodology with Highly Predictable Parasitics," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/24, 1998.
• M. Sgroi, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Quasi-Static Scheduling of Free-Choice Petri Nets," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/9, 1998.
• T. Shiple, R. Ranjan, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "Deciding State Reachability for Large FSMs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/73, 1997.
• A. Narayan, A. Isles, J. Jain, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Reachability Analysis Using Partitioned- ROBDDs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/27, 1997.
• P. Buch, A. Narayan, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Logic Synthesis for Large Pass Transistor Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/26, 1997.
• W. Gosti, T. Villa, A. Saldanha, and A. L. Sangiovanni-Vincentelli, "Input Encoding for Minimum BDD Size: Theory and Experiments," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/22, 1997.
• R. von Hanxleden, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Co-Design of a Fault-Tolerant Communication Protocol--A Case Study," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/13, 1997.
• E. A. Lee and A. L. Sangiovanni-Vincentelli, "A Denotational Framework for Comparing Models of Computation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/11, 1997. [abstract]
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Multi-Valued Decision Diagrams for Logic Synthesis and Verification," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/75, 1996.
• E. Goldberg, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Theory and Algorithms for Face Hypercube Embedding," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/74, 1996.
• L. Carloni, P. McGeer, A. Saldanha, and A. L. Sangiovanni-Vincentelli, "Trace Driven Logic Synthesis - Application to Power Minimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/62, 1996.
• L. Carloni, T. Villa, T. Kam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Generation of a Minimal STG from an Implicit Cover," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/40, 1996.
• E. A. Lee and A. L. Sangiovanni-Vincentelli, "The Tagged Signal Model A Preliminary Version of a Denotational Framework for Comparing Models of Computation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/33, 1996.
• T. Villa, T. Kam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "State Minimization of FSM's with Implicit Techniques," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/17, 1996.
• A. Oliveira, L. Carloni, T. Villa, and A. L. Sangiovanni-Vincentelli, "Exact Minimization of Binary Decision Diagrams Using Implicit Techniques," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/16, 1996.
• C. Passerone, M. Chiodo, W. Gosti, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Evaluation of Trade-Offs in the Design of Embedded Systems Via Co-Simulation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/12, 1996.
• J. Sanghavi, R. Ranjan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Binary Decision Diagrams on Network of Workstations," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/9, 1996.
• T. Villa, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Symbolic Two-Level Minimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/109, 1995.
• T. Villa, T. Kam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Explicit and Implicit Algorithms for Binate Covering Problems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/108, 1995.
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Theory and Algorithms for State Minimization of Non-Deterministic FSM's," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/107, 1995.
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Implicit Computation of Compatible Sets for State Minimization of ISFSM's," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/106, 1995.
• The VIS Group, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "VIS: A System for Verification and Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/104, 1995.
• A. Narayan, S. Khatri, J. Jain, M. Fujita, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Overcoming Memory Constraints in ROBDD Construction by Functional Decomposition and Partitioning," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/91, 1995.
• R. Ranjan, J. Sanghavi, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "High Performance BDD Package Based on Exploiting Memory Hierarchy," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/81, 1995.
• H. Sheng, R. Guerrieri, and A. L. Sangiovanni-Vincentelli, "Three-Dimensional Monte Carlo Device Simulation for Massively Parallel Architectures," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/53, 1995. [abstract]
• H. Sheng, R. Guerrieri, and A. L. Sangiovanni-Vincentelli, "Parallel and Distributed Three-Dimensional Monte Carlo Semiconductor Device Simulation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/52, 1995. [abstract]
• A. Narayan, S. Khatri, J. Jain, M. Fujita, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Compositional Techniques for Mixed Bottom-Up/Top-Down Constructions of ROBDDs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/51, 1995. [abstract]
• S. Khatri, A. Narayan, S. Krishnan, K. McMillan, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "An Engineering Change Methodology Using Simulation Relations," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/50, 1995. [abstract]
• J. Jain, A. Narayan, C. Coelho, S. Khatri, A. L. Sangiovanni-Vincentelli, R. K. Brayton, and M. Fujita, "Combining Top-Down and Bottom-Up Approaches for ROBDD Construction," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/30, 1995. [abstract]
• T. Villa, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Advances in Encoding for Logic Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/19, 1995.
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Implicit State Minimization of Non-Deterministic FSM's," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/18, 1995.
• F. Balarin, R. K. Brayton, S. Cheng, D. Kirkpatrick, A. L. Sangiovanni-Vincentelli, and E. Wu, "A Methodology for Formal Verification of Real-Time Systems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/11, 1995.
• M. Chiodo, P. Giusto, A. Jurecska, L. Lavagno, K. Suzuki, E. Sentovich, H. Hsieh, and A. L. Sangiovanni-Vincentelli, "Synthesis of Software Programs for Embedded Control Applications," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/87, 1994.
• A. Aziz, T. Shiple, V. Singhal, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Formula-Dependent Equivalence for Compositional CTL Model Checking," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/78, 1994.
• C. Charbon, G. Holmlund, A. L. Sangiovanni-Vincentelli, and B. Donecker, "A Performance-Driven Router for RF and Microwave Analog Circuit Design," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/40, 1994.
• F. Balarin and A. L. Sangiovanni-Vincentelli, "On the Automatic Computation of Network Invariants," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/18, 1994.
• C. Wawrukiewicz, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Sequential Test Pattern Generation: Using Implicit STG Traversal Techniques to Generate Tests and Identify Redundancies in Sequential Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/4, 1994. [abstract]
• T. Shiple, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Computing Boolean Expressions with OBDDs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/84, 1993. [abstract]
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A Fully Implicit Algorithm for Exact State Minimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/79, 1993. [abstract]
• T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Implicit Generation of Compatibles for Exact State Minimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/60, 1993. [abstract]
• T. Shiple, R. Hojati, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "Heuristic Minimization of BDDs, Using Don't Cares," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/58, 1993. [abstract]
• M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Synthesis of Mixed Software-Hardware Implementations from CFSM Specifications," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/49, 1993. [abstract]
• M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "A Formal Specification Model for Hardware/Software Codesign," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/48, 1993. [abstract]
• W. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Exact Minimum Delay Computation and Clock Frequencies," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/40, 1993. [abstract]
• W. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/6, 1993. [abstract]
• W. Lam, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Delay Fault Coverage, Test Set Size, and Performance Tradeoffs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/119, 1992.
• M. Chiodo and A. L. Sangiovanni-Vincentelli, "Design Methods for Reactive Real-Time Systems Codesign," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/116, 1992.
• P. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Combinational Test Generation Using Satisfiability," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/112, 1992.
• N. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Graph Algorithms for Efficient Clock Schedule Optimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/79, 1992.
• A. Yakovlev, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "A Unified Signal Transition Graph Model," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/78, 1992.
• P. McGeer, A. Saldanha, P. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Delay Models and Sensitization Criteria in the False Path Problem," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/63, 1992.
• W. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Exact Delay Computation with Timed Boolean Functions," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/57, 1992.
• W. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Minimum Cycle Time of Synchronous Circuit with Bounded Delays," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/56, 1992.
• M. Chiodo, T. Shiple, A. L. Sangiovanni-Vincentelli, and R. K. Brayton, "Automatic Reduction in CTL Compositional Model Checking," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/55, 1992.
• E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/41, 1992. [abstract]
• L. Lavagno, C. Moon, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A Novel Framework for Solving the State Assignment Problem for Event-Based Specifications," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/19, 1992.
• H. Savoj, M. Silva, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Boolean Matching in Logic Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/15, 1992.
• F. Balarin and A. L. Sangiovanni-Vincentelli, "Formal Verification of Timing Constrained Finite-State Systems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/8, 1992. [abstract]
• R. K. Brayton, M. Chiodo, R. Hojati, T. Kam, K. Kodandapani, R. Kurshan, S. Malik, A. L. Sangiovanni-Vincentelli, E. Sentovich, T. Shiple, K. Singh, and H. Wang, "BLIF-MV: An Interchange Format for Design Verification and Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/97, 1991.
• K. Keutzer, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Synthesis for Testability Techniques for Asynchronous Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/77, 1991.
• A. Saldanha, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A Framework for Satisfying Input and Output Encoding Constraints," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/110, 1990.
• L. Lavagno, K. Keutzer, and A. L. Sangiovanni-Vincentelli, "Synthesis of Verifiably Hazard-Free Asynchronous Control Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/99, 1990.
• L. Lavagno, S. Malik, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/68, 1990.
• R. McGeer, R. K. Brayton, R. Rudell, and A. L. Sangiovanni-Vincentelli, "Extended Stuck-Fault Testability for Combinational Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M89/87, 1989.
• S. Malik, E. Sentovich, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M89/28, 1989.
• A. Kramer and A. L. Sangiovanni-Vincentelli, "Optimization Techniques for Neural Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M89/1, 1989.
• S. Malik, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Encoding Symbolic Inputs for Multi-Level Logic Implementation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M88/69, 1988.
• S. Devadas, H. Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Irredundant Sequential Machines Via Optimal Logic Synthesis," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M88/52, 1988.
• S. Devadas, H. Tony Ma, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A Synthesis and Optimization Procedure for Fully Testable Sequential Machines," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M88/14, 1988.
• H. T. Ma, S. Devadas, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Test Generation for Sequential Finite State Machines," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/36, 1987.
• J. Burns, A. Casotto, M. Igusa, F. Marron, F. Romeo, A. L. Sangiovanni-Vincentelli, C. Sechen, H. Shin, G. Srinath, and H. Yaghutiel, "MOSAICO: An Integrated Macro-Cell Layout System," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/7, 1987.
• A. R. Newton and A. L. Sangiovanni-Vincentelli, "Computer-Aided Design for VLSI Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M86/16, 1986.
• J. White, F. Odeh, A. L. Sangiovanni-Vincentelli, and A. Ruehli, "Waveform Relaxation: Theory and Practice," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M85/65, 1985. [abstract]
• D. Mitra, F. Romeo, and A. L. Sangiovanni-Vincentelli, "Convergence and Finite-Time Behavior of Simulated Annealing," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M85/23, 1985.
• F. Romeo and A. L. Sangiovanni-Vincentelli, "Probabilistic Hill Climbing Algorithms: Properties and Applications," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M84/34, 1984.

Patents

• R. Passerone, J. A. Rowson, and A. Sangiovanni-Vincentelli, "System and method for automatically synthesizing interfaces between incompatible protocols," U.S. Patent 7,136,947. Nov. 2006.
• P. C. McGeer, A. Saldanha, and A. Sangiovanni-Vincentelli, "System and method for simulating discrete functions using ordered decision arrays," U.S. Patent 5,752,000. May 1998.

Talks or presentations

• A. L. Sangiovanni-Vincentelli, L. Carloni, J. Cong, D. D. Gajski, A. Kahng, R. Marculescu, and J. Roychowdhury, "The Core Theme," presented at GSRC Workshop, Yorktown Heights, NY, March 2008.
• C. Bin, S. Dabas, A. Pinto, S. Srivastava, J. Roychowdhury, and A. L. Sangiovanni-Vincentelli, "Hybrid System Simulation and Abstraction: MetroSPICE++," presented at GSRC Annual Symp., Sep. 2007.
• X. Lai, S. Srivastava, C. Bin, Z. Wang, C. Gu, S. Dabas, J. Roychowdhury, A. Pinto, A. L. Sangiovanni-Vincentelli, S. Gambini, and J. M. Rabaey, "MetroSPICE++ and CollabRadio: Synergistic Activities," presented at GSRC Joint Alternative/Core Workshop, June 2007.
• S. Dabas, X. Lai, S. Srivastava, J. M. Rabaey, A. L. Sangiovanni-Vincentelli, J. Roychowdhury, G. B. Meil, M. LaBouff, A. Srivastava, A. Pinto, and T. Mei, "Hybrid System Simulation: MetroSPICE++ (and CollabRadio Design Driver)," presented at GSRC Quarterly Workshop, San Francisco, CA, July 2006.