Faculty Publications - Borivoje Nikolic

Books

J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Pearson Education, 2003.
J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2 ed., Prentice Hall Electronics and VLSI Series, Upper Saddle River, NJ: Prentice Hall/Pearson Education, 2003.

D. Markovic, B. Nikolic, and R. W. Brodersen, "Power and area minimization for multidimensional signal processing," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 922-934, April 2007.
H. Liu, V. Dai, A. Zakhor, and B. Nikolic, "Reduced complexity compression algorithms for direct-write maskless lithography systems," SPIE J. Micro/Nanolithography, MEMS and MOEMS, vol. 6, no. 1, pp. 13007-1-12, Jan. 2007.
J. M. Rabaey, F. De Bernardinis, A. Niknejad, and B. Nikolic, "Embedding mixed-signal design in systems-on-chip," Proceedings of the IEEE, vol. 94, pp. 1070-1088, June 2006.
Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 2004.
D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods for true energy-performance optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.
Y. Shimazaki, R. Zlatanovici, and B. Nikolic, "A shared-well dual-supply-voltage 64-bit ALU," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 494-500, March 2004.
E. Yeo, B. Nikolic, and V. Anantharam, "Iterative decoder architectures," IEEE Communications Magazine, vol. 41, no. 8, pp. 132-140, Aug. 2003.
E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels," IEEE Trans. Magnetics, vol. 37, no. 2, pt. 1, pp. 748-755, March 2001.

L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, and B. Nikolic, "Evaluation of the Low Frame Error Rate Performance of LDPC Codes Using Importance Sampling," Information Theory Workshop, 2007. ITW '07. IEEE, 2007, pp. 202-207.
L. Dolecek, Z. Zhengya, V. Anantharam, M. Wainwright, and B. Nikolic, "Analysis of absorbing sets for array-based LDPC codes.," in 2007 IEEE International Conference on Communications., 2007, pp. 6261-6268.
H. Liu, V. Dai, A. Zakhor, and B. Nikolic, "Reduced complexity compression algorithms for direct-write maskless lithography systems," in Proc. SPIE: Emerging Lithographic Technologies X, M. J. Lercel, Ed., Vol. 6151, Bellingham, WA: SPIE, 2006, pp. 1-14.
Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED '05, Piscataway, NJ: IEEE, 2005, pp. 2-7.
B. Nikolic, B. Wild, V. Dai, Y. A. Shroff, B. Warlick, A. Zakhor, and W. G. Oldham, "Layout decompression chip for maskless lithography," in Proc. SPIE: Emerging Lithographic Technologies VIII, R. S. Mackay, Ed., Vol. 5374, Bellingham, WA: SPIE, 2004, pp. 1092-1099.
E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "High throughput low-density parity-check decoder architectures," in Proc. 2001 IEEE Global Telecommunications Conf. (GLOBECOM '01), Vol. 5, Piscataway, NJ: IEEE Press, 2001, pp. 3019-3024.

M. M. T. Leung, L. K. C. Fu, B. Nikolic, and J. K. S. Chiu, "Simplified branch metric and method," U.S. Patent 6,704,903. March 2004.
W. Jia and B. Nikolic, "Sense amplifier-based flip-flop with asynchronous set and reset," U.S. Patent 6,633,188. Oct. 2003.
B. Nikolic, L. Fu, M. Leung, V. G. Oklobdzija, and R. Yamasaki, "Reduced-complexity sequence detection," U.S. Patent 6,553,541. April 2003.
B. Nikolic and W. Jia, "Sense amplifier based flip-flop," U.S. Patent 6,107,853. Aug. 2000.
B. Nikolic and M. Leung, "Sliding block (rate 8/9) trellis code for magnetic recording," U.S. Patent 6,081,210. June 2000.