Faculty Publications - Ernest S. Kuh

Books

• L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits, McGraw-Hill Series in Electrical Engineering: Circuits and Systems, New York: McGraw-Hill, 1987. [abstract]
• T. C. Hu and E. S. Kuh, Eds., VLSI Circuit Layout: Theory and Design, IEEE Press Selected Reprint Series, New York: Institute of Electrical and Electronics Engineers, 1985. [abstract]
• C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York, NY: McGraw-Hill, 1969. [abstract]
• E. S. Kuh and R. A. Rohrer, Theory of Linear Active Networks, Holden-Day Series in Information Systems, San Francisco, CA: Holden-Day, Inc., 1967. [abstract]
• E. S. Kuh and D. O. Pederson, Principles of Circuit Synthesis, McGraw-Hill Electrical and Electronic Engineering Series, New York: McGraw-Hill, 1959. [abstract]

Selected Articles in journals or magazines

• R. Tsay, E. S. Kuh, and C. Hsu, "PROUD: A sea-of-gates placement algorithm," IEEE Design & Test of Computers, vol. 5, no. 6, pp. 44-56, Dec. 1988.
• E. S. Kuh and R. A. Rohrer, "The state-variable approach to network analysis," Proc. IEEE, vol. 53, no. 7, pp. 672-686, July 1965.

Selected Articles in conference proceedings

• S. Lin and E. S. Kuh, "Circuit simulation for large interconnected IC networks," in Proc. IFIP TC10/WG 10.5 Intl. Conf. on Very Large Scale Integration, K. Yanagawa and P. A. Ivey, Eds., Amsterdam, The Netherlands: North-Holland Publishing Company, 1993, pp. 333-342.
• N. P. Chen, C. P. Hsu, and E. S. Kuh, "The Berkeley Building-Block (BBL) layout system for VLSI design," in Proc. IFIP TC WG 10.5 Intl. Conf. on Very Large Scale Integration, F. Anceau and E. J. Aas, Eds., Amsterdam, The Netherlands: North-Holland Publishing Company, 1983, pp. 37-44.

Technical Reports

• T. A. Henzinger, S. Qadeer, S. Rajamani, S. Tasiran, J. Wang, and E. S. Kuh, "An Assume-Guaranteee Rule for Checking Simulation for Multipoint Moment Matching of Multiport Distributed Interconnect Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/13, 1999.
• Q. Yu, J. Wang, and E. S. Kuh, "Passive Model Order Reduction Algorithm for Multipoint Moment Matching of Multiport Distributed Interconnect Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/13, 1998.
• Q. Yu and E. S. Kuh, "Reduced Order Model of Transmission Lines by Multiple Points Moment Matching and Passivity Preservation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/70, 1997.
• T. Xue, E. S. Kuh, and D. Wang, "Post Global Routing Crosstalk Risk Estimation and Reduction," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/13, 1996.
• H. Esbensen and E. S. Kuh, "An Interactive Floorplanner for Design Space Exploration," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M96/4, 1996.
• H. Esbensen and E. S. Kuh, "Design Space Exploration for Building- Block Placements," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/84, 1995.
• P. Buch and E. S. Kuh, "SYMPHONY: An Efficient Mixed Signal Circuit Simulator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/24, 1995.
• H. Esbensen and E. S. Kuh, "An IC/MCM Timing-Driven Placement Algorithm Featuring Explicit Design Space Exploration," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/20, 1995.
• Q. Yu and E. S. Kuh, "An Accurate Time Domain Interconnect Model of Transmission Line Networks," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M95/10, 1995.
• P. Buch, S. Lin, V. Nagasamy, and E. S. Kuh, "Techniques for Fast Circuit Simulation Applied to Power Estimation of CMOS Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/98, 1994.
• C. Hough, T. Xue, and E. S. Kuh, "New Approaches for On-Chip Power Switching Noise Reduction," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/94, 1994.
• Q. Yu and E. S. Kuh, "Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M94/20, 1994.
• N. Bhat, K. Chaudhary, and E. S. Kuh, "Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/42, 1993. [abstract]
• M. Shih and E. S. Kuh, "Quadratic Boolean Programming for Performance-Driven System Partitioning," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/19, 1993. [abstract]
• M. Shih, E. S. Kuh, and R. Tsay, "Integer Programming Techniques for Multiway System Partitioning Undertiming and Capacity Constraints," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M92/81, 1992.
• A. Srinivasan, K. Chaudhary, and E. S. Kuh, "RITUAL: A Performance Driven Placement Algorithm," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/103, 1991.
• A. Srinivasan, K. Chaudhary, and E. S. Kuh, "RITUAL An Algorithm for Performance-Driven Placement of Cell-Based ICs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/47, 1991. [abstract]
• D. Wang and E. S. Kuh, "Novel Routing Schemes for IC Layout Part II: Three-Layer Channel Routing," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/102, 1990.
• D. Wang and E. S. Kuh, "Novel Routing Schemes for IC Layout Part I: Two-Layer Channel Routing," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/101, 1990.
• M. Jackson, A. Srinivasan, and E. S. Kuh, "A Novel Approach to IC Performance Optimization by Clock Routing," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/27, 1990. [abstract]
• X. Xiong and E. S. Kuh, "A Unified Approach to the Via Minimization Problem," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/80, 1987.
• R. Tsay, E. S. Kuh, and C. Hsu, "PROUD: A Fast Sea-of-Gates Placement Algorithm," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/79, 1987.
• R. Tsay and E. S. Kuh, "A Unified Approach to Circuit Partitioning and Placement," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M86/8, 1986.
• W. Dai, T. Asano, and E. S. Kuh, "Building Block Layout: Routing Region Definition and Ordering Scheme," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M85/14, 1985.
• N. Chen, C. Chen, C. Hsu, H. Chen, E. S. Kuh, and M. Sadowska, "BBL.2 User's Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M85/2, 1985. [abstract]
• C. Cheng and E. S. Kuh, "RAMP: Gate-Array, Standard-Cell and Masterimage Placement Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M84/71, 1984. [abstract]
• N. Chen, C. Hsu, H. Chen, E. S. Kuh, and M. Marek-Sadowska, "BBL User's Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M83/68, 1983.
• C. Cheng and E. S. Kuh, "Module Placement Based on Resistive Network Optimization," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M83/35, 1983.
• T. T. Tarng, M. Marek-Sadowska, and E. S. Kuh, "An Efficient Single-Row Routing Algorithm," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M83/34, 1983.
• N. Chen, C. Hsu, and E. S. Kuh, "Berkeley Building-Block Layout System for VLSI Design," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M83/10, 1983.