Faculty Publications - Tsu-Jae King Liu

Articles in journals or magazines

• S. Xiong, T. King Liu, and J. Bokor, "A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, Aug. 2005.
• M. Eyoum and T. King Liu, "Low resistance silicon-germanium contact technology for modular integration of MEMS with electronics," J. Electrochemical Society, vol. 151, no. 3, pp. J21-J25, Feb. 2004.
• A. E. Franke, J. M. Heck, T. King Liu, and R. T. Howe, "Polycrystalline silicon-germanium films for integrated microsystems," J. Microelectromechanical Systems, vol. 12, no. 2, pp. 160-171, April 2003.
• C. Kuo, T. King Liu, and C. Hu, "A capacitorless double-gate DRAM cell," IEEE Electron Device Letters, vol. 23, no. 6, pp. 345-347, June 2002.
• Y. Choi, T. King Liu, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, March 2002.
• Y. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. King Liu, J. Bokor, and C. Hu, "Paul Rappaport Award for 2002: Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 279-286, Feb. 2002.
• D. Hisamoto, W. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. King Liu, J. Bokor, and C. Hu, "FinFET--A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.

Articles in conference proceedings

• Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED '05, Piscataway, NJ: IEEE, 2005, pp. 2-7.
• P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. King Liu, "FinFET SONOS flash memory for embedded applications," in 2003 Intl. Electron Devices Meeting (IEDM '03). Technical Digest, Piscataway, NJ: IEEE Press, 2003, pp. 609-612.
• M. She, H. Takeuchi, and T. King Liu, "Improved SONOS-type flash memory using HfO2 as trapping layer," in 19th IEEE Non-Volatile Semiconductor Memory Workshop Digest, Piscataway, NJ: IEEE, 2003, pp. 53-55.
• B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
• B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, T. King Liu, J. Bokor, M. Lin, and D. Kyser, "FinFET scaling: Towards 10nm gate length," in IEDM '02 Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
• J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. King Liu, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," in 2000 Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2000, pp. 57-60.
• S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W. Sigmon, Y. J. Tung, and T. King Liu, "Polysilicon thin film transistors fabricated at 100°C on a flexible plastic substrate," in International Electron Devices Meeting 1998 Technical Digest, Piscataway, NJ: IEEE, 1998, pp. 257-260.

Patents

• T. King, "Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects," U.S. Patent 7,187,028. March 2007.
• T. King, "Method of forming a negative differential resistance device," U.S. Patent 7,186,621. March 2007.
• T. King and V. Moroz, "Integrated circuit on corrugated substrate," U.S. Patent 7,190,050. March 2007.
• T. King, "Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET," U.S. Patent 7,186,619. March 2007.
• I. Polishchuk, P. Ranade, T. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," U.S. Patent 7,141,858. Nov. 2006.
• T. King, "Method of forming a negative differential resistance device," U.S. Patent 7,113,423. Sep. 2006.
• T. King and D. K. Y. Liu, "CMOS compatible process for making a charge trapping device," U.S. Patent 7,109,078. Sep. 2006.
• T. King, "Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device," U.S. Patent 7,095,659. Aug. 2006.
• T. King, "Negative differential resistance (NDR) elements and memory device using the same," U.S. Patent 7,098,472. Aug. 2006.
• Q. Ji, K. Standiford, T. King, and K. Leung, "Ion beam extractor with counterbore," U.S. Patent 7,084,407. Aug. 2006.
• T. King, "Methods of testing/stressing a charge trapping device," U.S. Patent 7,060,524. June 2006.
• T. King and D. K. Y. Liu, "Charge trapping device," U.S. Patent 7,067,873. June 2006.
• T. King and D. K. Y. Liu, "Charge trapping device," U.S. Patent Application. May 2006.
• T. King, "Two terminal silicon based negative differential resistance device," U.S. Patent 7,016,224. March 2006.
• T. King, "Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)," U.S. Patent 7,012,833. March 2006.
• T. King, "Enhanced read and write methods for negative differential resistance (NDR) based memory device," U.S. Patent 7,012,842. March 2006.
• T. King, "Charge trapping device and method of forming the same," U.S. Patent 7,015,536. March 2006.
• T. King, "N-channel pull-up element and logic circuit," U.S. Patent 7,005,711. Feb. 2006.
• T. King, "Method of making memory cell utilizing negative differential resistance devices," U.S. Patent 6,990,016. Jan. 2006.
• T. King, "Process for controlling performance characteristics of a negative differential resistance (NDR) device," U.S. Patent 6,979,580. Dec. 2005.
• T. King, "Method of forming a negative differential resistance device," U.S. Patent 6,980,467. Dec. 2005.
• T. King and D. K. Y. Liu, "CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same," U.S. Patent 6,972,465. Dec. 2005.
• T. King and D. K. Y. Liu, "Variable threshold semiconductor device and method of operating same," U.S. Patent 6,969,894. Nov. 2005.
• T. King, "Charge trapping pull up element," U.S. Patent 6,956,262. Oct. 2005.
• T. King, "Negative differential resistance pull up element for DRAM," U.S. Patent Application. Aug. 2005.
• T. King, "Negative differential resistance load element," U.S. Patent 6,933,548. Aug. 2005.
• T. King and V. Moroz, "Segmented channel MOS transistor," U.S. Patent Application. July 2005.
• T. King and V. Moroz, "Method of IC production using corrugated substrate," U.S. Patent Application. July 2005.
• T. King, "Negative differential resistance (NDR) based memory device with reduced body effects," U.S. Patent 6,912,151. June 2005.
• K. Shin and T. King, "Complementary field-effect transistors having enhanced performance with a single capping layer," U.S. Patent Application. June 2005.
• M. She and T. King, "Two bit/four bit SONOS flash memory cell," U.S. Patent Application. May 2005.
• T. King, "Negative differential resistance pull up element," U.S. Patent 6,894,327. May 2005.
• H. Takeuchi, E. P. Quevy, T. King, and R. T. Howe, "Damascene process for use in fabricating semiconductor structures having micro/nano gaps," U.S. Patent Application. May 2005.
• T. King, "Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects," U.S. Patent 6,864,104. March 2005.
• T. King, "Negative differential resistance (NDR) memory cell with reduced soft error rate," U.S. Patent 6,861,707. March 2005.
• T. King, "Negative differential resistance (NDR) memory device with reduced soft error rate," U.S. Patent 6,853,035. Feb. 2005.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," U.S. Patent 6,855,994. Feb. 2005.
• T. King, "Charge trapping device and method of forming the same," U.S. Patent 6,849,483. Feb. 2005.
• T. King, "Enhanced read and write methods for negative differential resistance (NDR) based memory device," U.S. Patent 6,847,562. Jan. 2005.
• T. King, "Negative differential resistance (NDR) memory device with reduced soft error rate," U.S. Patent Application. Dec. 2004.
• T. King, "Process for controlling performance characteristics of a negative differential resistance (NDR) device," U.S. Patent Application. Nov. 2004.
• T. King, "Method of making adaptive negatie differential resistance device," U.S. Patent Application. Nov. 2004.
• M. She and T. King, "Flash memory devices using large electron affinity material for charge trapping," U.S. Patent Application. Nov. 2004.
• T. King, "Adaptive negative differential resistance device," U.S. Patent 6,812,084. Nov. 2004.
• T. King, "Methods of testing/stressing a charge trapping device," U.S. Patent 6,806,117. Oct. 2004.
• T. King, "Negative differential resistance (NDR) elements and memory device using the same," U.S. Patent 6,795,337. Sep. 2004.
• I. Polishchuk, P. Ranade, T. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," U.S. Patent 6,794,234. Sep. 2004.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," U.S. Patent 6,753,229. June 2004.
• T. King, "Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET," U.S. Patent 6,754,104. June 2004.
• T. King, "Negative differential resistance (NDR) element and memory with reduced soft error rate," U.S. Patent 6,727,548. April 2004.
• T. King, "Memory cell using negative differential resistance field effect transistors," U.S. Patent 6,724,655. April 2004.
• T. King, "Field effect transistor pull-up/load element," U.S. Patent 6,724,024. April 2004.
• T. King and D. K. Y. Liu, "Charge trapping device and method for implementing a transistor having a configurable threshold," U.S. Patent 6,700,115. March 2004.
• T. King and D. K. Y. Liu, "Negative differential resistance (NDR) device and method of operating same," U.S. Patent 6,686,631. Feb. 2004.
• T. King, "Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode," U.S. Patent 6,686,267. Feb. 2004.
• T. King and D. K. Y. Liu, "Method for configuring a device to include a negative differential resistance (NDR) characteristic," U.S. Patent 6,693,027. Feb. 2004.
• T. King and D. K. Y. Liu, "Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process," U.S. Patent 6,680,245. Jan. 2004.
• T. King, "Method of operating a dual mode FET & logic circuit having negative differential resistance mode," U.S. Patent 6,664,601. Dec. 2003.
• T. King, "Charge pump for negative differential resistance transistor," U.S. Patent 6,594,193. July 2003.
• T. King and D. K. Y. Liu, "CMOS compatible process for making a tunable negative differential resistance (NDR) device," U.S. Patent 6,596,617. July 2003.
• T. King, "Negative differential resistance field effect transistor (NDR-FET) and circuits using the same," U.S. Patent 6,559,470. May 2003.
• T. King, "Negative differential resistance (NDR) element and memory with reduced soft error rate," U.S. Patent 6,567,292. May 2003.
• T. King, "Dual mode FET & logic circuit having negative differential resistance mode," U.S. Patent 6,518,589. Feb. 2003.
• T. King and D. K. Y. Liu, "CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same," U.S. Patent 6,512,274. Jan. 2003.
• T. King and D. K. Y. Liu, "Charge trapping device and method for implementing a transistor having a negative differential resistance mode," U.S. Patent 6,479,862. Nov. 2002.
• A. Franke, R. T. Howe, and T. King, "Polycrystalline silicon-germanium films for micro-electromechanical systems application," U.S. Patent 6,448,622. Sep. 2002.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," Aug. 2002.
• C. Hu, T. King, V. Subramanian, L. Chang, X. Huang, Y. Choi, J. T. Kedzierski, N. Lindert, J. Bokor, and W. Lee, "FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture," U.S. Patent 6,413,802. July 2002.
• R. T. Howe, A. Franke, and T. King, "Polycrystalline silicon germanium films for forming micro-electromechanical systems," U.S. Patent 6,210,988. April 2001.
• T. King and J. H. Ho, "Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates," U.S. Patent 5,893,949. April 1999.
• T. King and J. H. Ho, "Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates," U.S. Patent 5,707,744. Jan. 1998.
• T. King and M. G. Hack, "Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions," U.S. Patent 5,401,982. March 1995.
• K. C. Saraswat and T. King, "Low temperature germanium-silicon on insulator thin-film transistor," U.S. Patent 5,250,818. Oct. 1993.