Faculty Publications - Tsu-Jae King Liu

Book chapters or sections

• T. King Liu and L. Chang, "Transistor scaling to the limit," in Into the Nano Era: Moore's Law Beyond Planar Silicon CMOS, H. R. Huff, Ed., Springer Series in Materials Science, Vol. 106, Berlin, Germany: Springer-Verlag, 2008, pp. 191-223.
• A. Carlson and T. King Liu, "Negative and iterated spacer lithography processes for low variability and ultra-dense integration," in Optical Microlithography XXI, H. J. Levinson and M. V. Dusa, Eds., SPIE -- Society of Photo-Optical Instrumentation Engineers, Vol. 6924, Bellingham, WA: SPIE -- The International Society for Optical Engineering, 2008, pp. 69240B-1-9.
• K. Patel, T. King Liu, and C. J. Spanos, "Impact of gate line edge roughness on double-gate FinFET performance variability," in Design for Manufacturability through Design-Process Integration II, V. K. Singh and M. L. Rieger, Eds., Proceedings of SPIE, Vol. 6925, Bellingham, WA: SPIE -- Society of Photo-Optical Instrumentation Engineers, 2008, pp. 1I-1-10.
• B. C. Y. Lin, T. King Liu, and R. S. Muller, "Poly-SiGe MEMS actuators for adaptive optics," in MEMS/MOEMS Components and Their Applications IIII, S. S. Olivier, S. A. Tadigadapa, and A. K. Henning, Eds., Proceedings of SPIE, Vol. 6113, Bellingham, WA: SPIE -- Society of Photo-Optical Instrumentation Engineers, 2006, pp. 61130S-1-7.

Articles in journals or magazines

• R. A. Vega and T. King Liu, "A comparative study of dopant-segregated Schottky and raised source/drain double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2665-2677, Oct. 2008.
• R. Nathaneal, W. Xiong, C. R. Cleavelin, and T. King Liu, "Impact of gate-induced strain on MuGFET reliability," IEEE Electron Device Letters, vol. 29, no. 8, pp. 916-919, Aug. 2008.
• X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda, C. Shin, and T. King Liu, "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap," IEEE Electron Device Letters, vol. 29, no. 5, pp. 491-493, May 2008.
• G. Liu, P. Haldi, T. King Liu, and A. Niknejad, "Fully integrated CMOS power amplifier with efficiency enhancement at power back-off," IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 600-609, March 2008.
• G. K. Fedder, R. T. Howe, T. King Liu, and E. P. Quevy, "Technologies for cofabricating MEMS and electronics (Invited Paper)," Proc. IEEE, vol. 96, no. 2, pp. 306-322, Feb. 2008.
• J. J. Welser, S. Kosonocky, T. King Liu, T. Sakurai, R. Thewes, and B. Zhao, "Guest Editors' Commentary: Special Issue on Device Technologies and Circuit Techniques for Power Management," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 4-7, Jan. 2008.
• Y. Yasuda, T. King Liu, and C. Hu, "Flicker-noise impact on scaling of mixed-signal CMOS with HfSiON," IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 417-422, Jan. 2008.
• W. Xiong, C. R. Cleavelin, C. H. Hsu, M. Ma, K. Schruefer, K. Von Armin, T. Schulz, I. Cayrefourcq, C. mazure, P. Patruno, M. Kennard, K. Shin, X. Sun, T. King Liu, K. Cherkaoui, and J. P. Colinge, "Intrinsic advantages of SOI multiple-gate MOSFET (MuGFET) for low power applications (Invited)," ECS Trans., vol. 6, no. 4, pp. 59-69, 2007.
• D. Lee, T. Seidel, J. Dalton, and T. King Liu, "ALD refill of nanometer-scale gaps with high-k dielectric for advanced CMOS technologies," Electrochemical and Solid-State Letters, vol. 10, no. 9, pp. H257-259, 2007.
• X. Sun, Q. Lu, H. Takeuchi, S. Balasubramanian, and T. King Liu, "Selective enhancement of SiO2 etch rate by Ar ion implantation for improved etch depth control," Electrochemical and Solid-State Letters, vol. 10, no. 9, pp. D89-D91, 2007.
• R. A. Vega and T. King Liu, "Low pressure chemical vapor deposition in in-situ-doped n- and p-type $ Si sub {(1-x)} Ge sub x $ films at 425 degrees C," J. Electrochemical Society, vol. 154, no. 9, pp. H789-H793, Sep. 2007.
• W. Y. Choi, B. G. Park, J. D. Lee, and T. King Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007.
• J. Lai and T. King Liu, "Defect passivation by selenium ion implantation for poly-Si thin film transistors," IEEE Electron Device Letters, vol. 28, no. 8, pp. 725-727, Aug. 2007.
• A. Padilla, K. Shin, T. King Liu, J. W. Hyun, I. Yoo, and Y. Park, "Dual-bit gate-side-wall-storage FinFET NVM and new method of charge detection," IEEE Electron Device Letters, vol. 28, no. 6, pp. 502-505, June 2007.
• C. W. Low, T. King Liu, and R. T. Howe, "Characterization of polycrystalline silicon-germanium film deposition for modularly integrated MEMS applications," J. Microelectromechanical Systems, vol. 16, no. 1, pp. 68-77, Feb. 2007.
• Q. Lu and T. King Liu, "Trap energy levels association with indium and boron impurities in SiO2," Electrochemical and Solid-State Letters, vol. 9, no. 9, pp. G296-G298, 2006.
• D. Good, P. Wickboldt, and T. King Liu, "Defect passivation in poly-Si TFTs by ion implantation and pulsed laser annealing," IEEE Electron Device Letters, vol. 27, no. 10, pp. 840-842, Oct. 2006.
• K. Shin, W. Xiong, C. Y. Cho, C. R. Cleavelin, T. Schulz, K. Schruefer, P. Patruno, L. Smith, and T. King Liu, "Study of bending-induced strain effects on MuGFET performance," IEEE Electron Device Letters, vol. 27, no. 8, pp. 671-673, Aug. 2006.
• A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, C. Hu, and T. King Liu, "MOSFET hot-carrier reliabillity improvement by forward body bias," IEEE Electron Device Letters, vol. 27, no. 7, pp. 605-608, July 2006.
• W. Xiong, C. R. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, Y. M. Le Vaillant, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, and T. King Liu, "Impact of strained-silicon-on-insulator (sSOI), substrate on FinFET mobility," IEEE Electron Device Letters, vol. 27, no. 7, pp. 612-614, July 2006.
• A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, T. King Liu, and C. Hu, "MOSFET design of forward body biasing scheme," IEEE Electron Device Letters, vol. 27, no. 5, pp. 387-389, May 2006.
• L. Xu, C. P. Grigoropoulos, and T. King Liu, "High-performance thin-silicon-film transistors fabricated by double laser crystallization," J. Applied Physics, vol. 99, no. 3, pp. 034508-1-6, Feb. 2006.
• S. Xiong, T. King Liu, and J. Bokor, "A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, Aug. 2005.
• M. Eyoum and T. King Liu, "Low resistance silicon-germanium contact technology for modular integration of MEMS with electronics," J. Electrochemical Society, vol. 151, no. 3, pp. J21-J25, Feb. 2004.
• A. E. Franke, J. M. Heck, T. King Liu, and R. T. Howe, "Polycrystalline silicon-germanium films for integrated microsystems," J. Microelectromechanical Systems, vol. 12, no. 2, pp. 160-171, April 2003.
• C. Kuo, T. King Liu, and C. Hu, "A capacitorless double-gate DRAM cell," IEEE Electron Device Letters, vol. 23, no. 6, pp. 345-347, June 2002.
• Y. Choi, T. King Liu, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, March 2002.
• Y. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. King Liu, J. Bokor, and C. Hu, "Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel (Paul Rappaport Award for 2002)," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 279-286, Feb. 2002.
• D. Hisamoto, W. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. King Liu, J. Bokor, and C. Hu, "FinFET--A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.

Articles in conference proceedings

• P. Kalra, P. Majhi, H. H. Tseng, R. Jammy, and T. King Liu, "Optimization of flash annealing parameters to achieve ultra-shallow junctions for sub-45nm CMOS," in Doping Engineering for Front-End Processing: Proc. 2008 MRS Spring Meeting, B. J. Pawlak, M. L. Pelaz, M. Law, and K. Suguro, Eds., MRS Proceedings, Vol. 1070, Warrendale, PA: Materials Research Society, 2008, pp. 6 pg.
• H. Kam, T. King Liu, E. Alon, and M. Horowitz, "Circuit-Driven Requirements for CMOS-Replacement Devices," in IEEE International Electron Devices Meeting, 2008.
• P. Kalra, P. Majhi, H. H. Tseng, R. Jammy, and T. King Liu, "Infusion doping for sub-45nm CMOS technology nodes," in Proc. 17th Intl. Conf. on Ion Implantation Technology, E. G. Seebauer, S. B. Felch, A. Jain, and Y. V. Kondratenko, Eds., AIP Conference Proceedings: Materials Physics and Applications, Vol. 1066, Warrendale, PA: American Institute of Physics, 2008.
• P. Kalra, P. Majhi, H. H. Tseng, L. Larson, R. jammy, and T. King Liu, "USJ process challenges for sub-45nm CMOS (Invited)," in Proc. 17th Intl. Conf. on Ion Implantation Technology, E. G. Seebauer, S. B. Felch, A. Jain, and Y. V. Kondratenko, Eds., AIP Conference Proceedings: Materials Physics and Applications, Vol. 1066, Melville, NY: American Institute of Physics, 2008, pp. 55-62.
• F. Chen, H. Kam, D. Markovic, T. King Liu, V. Stojanovic, and E. Alon, "Integrated Circuit Design with NEM Relays," in IEEE/ACM International Conference on Computer-Aided Design, 2008.
• A. Carlson, Z. Guo, L. T. Pang, T. King Liu, and B. Nikolic, "Compensation of systematic variations through optimal biasing of SRAM wordlines," in Proc. 2008 Custom Integrated Circuits Conf. (CICC '08), Piscataway, NJ: IEEE Press, 2008.
• C. Shin, A. Carlson, X. sun, K. Jeon, and T. King Liu, "Tri-gate bulk MOSFET design for improved robustness to random dopant fluctuations," in Proc. IEEE 2008 Silicon Nanoelectronics Workshop, Piscataway, NJ: IEEE Press, 2008.
• A. Carlson, X. Sun, C. Shin, and T. King Liu, "SRAM yield and performance enhancements with tri-gate bulk MOSFETs," in Proc. IEEE 2008 Silicon Nanoelectronics Workshop, Piscataway, NJ: IEEE Press, 2008.
• A. Padilla, S. Lee, D. Carlton, and T. King Liu, "Enhanced endurace of dual-bit SONOS NVM cells using the GIDL read method," in 2008 Symp. on VLSI Technology Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2008, pp. 142-143.
• Z. Guo, A. Carlson, L. Pang, K. Duong, T. King Liu, and B. Nikolic, "Large-scale read/write margin measurement in 45nm CMOS SRAM arrays," in Proc. 2008 IEEE Symp. on VLSI Circuits, Piscataway, NJ: IEEE Press, 2008, pp. 42-43.
• H. H. Tseng, P. Kalra, J. Oh, P. Majhi, T. King Liu, and R. Jammy, "The Challenges and Progress of USJ Formation and Process Integration for 32nm Technology and Beyond (Keynote)," in Proc. 2008 Intl. Workshop on Junction Technology (IWJT '08), Piscataway, NJ: IEEE Press, 2008, pp. 3-6.
• P. Kalra, P. Majhi, D. Heh, G. Bersuker, C. Young, N. Vora, R. Harris, P. Kirsch, R. choi, M. Chang, J. Lee, H. Hwang, H. H. Tseng, R. Jimmy, and T. King Liu, "Impact of flash annealing on performance and reliability of high-k/metal-gate MOSFETs for sub-45nm CMOS," in 53rd IEEE Intl. Electon Devices Meeting (IEDM 2007) Technical Digest, Piscataway, NJ: IEEE Press, 2007, pp. 353-356.
• W. Y. Choi, H. Kam, D. Lee, J. Lai, and T. King Liu, "Compact nano-electro-mechanical non-volatile memory (NEMory) for 3D integration," in 53rd IEEE Intl. Electon Devices Meeting (IEDM 2007) Technical Digest, Piscataway, NJ: IEEE Press, 2007, pp. 603-606.
• C. H. Hsu, W. Xiong, C. T. Lin, Y. T. Huang, M. Ma, C. R. Cleavelin, P. Patruno, M. kennard, I. Cayrefourcq, K. Shin, and T. King Liu, "Multi-gate MOSFETs with dual contact etch stop liner stressors on tensile metal gate and strained silicon on insulator (sSOI)," in Proc. 2007 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '07), Piscataway, NJ: IEEE Press, 2007, pp. 2 pg.
• A. Padilla and T. King Liu, "Dual-bit SONOS FinFET non-volatile memory cell and new method of charge detection," in Proc. 2007 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '07), Piscataway, NJ: IEEE Press, 2007, pp. 2 pg.
• D. Lee, X. Sun, E. Quevy, R. T. Howe, and T. King Liu, "WetFET--A novel fluidic gate-dielectric transistor for sensor applications (Best Student Paper Award)," in Proc. 2007 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '07), Piscataway, NJ: IEEE Press, 2007, pp. 2 pg.
• K. Shin, S. Balasubramanian, X. Sun, and T. King Liu, "Strain engineering and body biasing for optimization of sub-45nm CMOS performance (Invited)," in Proc. MRS 2006 Spring Meeting, Warrendale, PA: Materials Research Society, 2006.
• V. Varadarajan, Y. Yasuda, S. Balasubramanian, and T. King Liu, "WireFET technology for 3-D integrated circuits," in 52nd Intl. Electron Devices Meeting (IEDM 2006) Technical Digest, Piscataway, NJ: IEEE Press, 2006, pp. 4 pg.
• H. Takeuchi, K. Shiraishi, and T. King Liu, "Role of oxygen states in high-k gate stack engineering (Invited)," in Proc. 8th Intl. Conf. on Solid-State and Integrated Circuit Technology (ICSICT-2006), T. A. Tang, G. P. Ru, and Y. L. Jiang, Eds., Piscataway, NJ: IEEE Press, 2006, pp. 388-391.
• K. Shiraishi, H. Takeuchi, Y. Akasaka, T. Nakayama, S. Miyazaki, T. Nakaoka, A. Ohta, H. Watanabe, N. Umezawa, K. Ohmori, P. Ahmet, K. Toii, T. Chikyow, Y. Nara, T. King Liu, H. Iwai, and K. Yamada, "Physics of interfaces between gate electrodes and high-k dielectrics (Invited)," in Proc. 8th Intl. Conf. on Solid-State and Integrated Circuit Technology (ICSICT-2006), T. A. Tang, G. P. Ru, and Y. L. Jiang, Eds., Piscataway, NJ: IEEE Press, 2006, pp. 384-387.
• A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. King Liu, and B. Nikolic, "FinFET SRAM with enhanced read/write margins," in Proc. 2006 IEEE Intl. SOI Conf. (SOI '06), Piscataway, NJ: IEEE Press, 2006, pp. 105-106.
• K. Shiraishi, Y. Akasaka, N. Umezawa, Y. Nara, K. Yamada, H. Takeuchi, H. Watanabe, T. Chikyow, and T. King Liu, "Theory of Fermi level pinning of high-k dielectrics," in Proc. 2006 Intl. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD '06), Piscataway, NJ: IEEE Press, 2006.
• G. Liu, T. King Liu, and A. Niknejad, "A 1.2V, 2.4GHz fully integrated linear CMOS power amplifier with efficiency enhancement," in Proc. 2006 IEEE Custom Integrated Circuits Conf. (CICC '06), Piscataway, NJ: IEEE Press, 2006, pp. 141-144.
• Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED '05, Piscataway, NJ: IEEE, 2005, pp. 2-7.
• P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. King Liu, "FinFET SONOS flash memory for embedded applications," in 2003 Intl. Electron Devices Meeting (IEDM '03). Technical Digest, Piscataway, NJ: IEEE Press, 2003, pp. 609-612.
• M. She, H. Takeuchi, and T. King Liu, "Improved SONOS-type flash memory using HfO2 as trapping layer," in 19th IEEE Non-Volatile Semiconductor Memory Workshop Digest, Piscataway, NJ: IEEE, 2003, pp. 53-55.
• B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
• B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, T. King Liu, J. Bokor, M. Lin, and D. Kyser, "FinFET scaling: Towards 10nm gate length," in IEDM '02 Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
• J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. King Liu, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," in 2000 Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2000, pp. 57-60.
• S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W. Sigmon, Y. J. Tung, and T. King Liu, "Polysilicon thin film transistors fabricated at 100°C on a flexible plastic substrate," in International Electron Devices Meeting 1998 Technical Digest, Piscataway, NJ: IEEE, 1998, pp. 257-260.

Technical Reports

• M. H. Cho, C. Shin, and T. King Liu, "Convex Channel Design for Improved Capacitorless DRAM Retention Time," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2009-147, Oct. 2009. [abstract]

Patents

• T. King Liu and V. Moroz, "Method of IC production using corrugated substrate," U.S. Patent 7,265,008. Sep. 2007. [abstract]
• T. King Liu, "Compact static memory cell with non-volatile storage capability," U.S. Patent 7,266,010. Sep. 2007. [abstract]
• T. King Liu, "Method of making adaptive negative differential resistance device," U.S. Patent 7,254,050. Aug. 2007. [abstract]
• H. Takeuchi, E. P. Quevy, T. King Liu, and R. T. Howe, "Damascene process for use in fabricating semiconductor structures having micro/nano gaps," U.S. Patent 7,256,107. Aug. 2007. [abstract]
• T. King Liu, "Segmented channel MOS transistor," U.S. Patent 7,247,887. July 2007. [abstract]
• T. King Liu, "Process for controlling performance characteristics of a negative differential resistance (NDR) device," U.S. Patent 7,220,636. May 2007. [abstract]
• T. King Liu and V. Moroz, "Integrated circuit on corrugated substrate," U.S. Patent 7,190,050. March 2007. [abstract]
• T. King, "Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects," U.S. Patent 7,187,028. March 2007. [abstract]
• T. King, "Method of forming a negative differential resistance device," U.S. Patent 7,186,621. March 2007.
• T. King, "Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET," U.S. Patent 7,186,619. March 2007.
• I. Polishchuk, P. Ranade, T. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," U.S. Patent 7,141,858. Nov. 2006.
• T. King, "Method of forming a negative differential resistance device," U.S. Patent 7,113,423. Sep. 2006.
• T. King and D. K. Y. Liu, "CMOS compatible process for making a charge trapping device," U.S. Patent 7,109,078. Sep. 2006.
• T. King, "Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device," U.S. Patent 7,095,659. Aug. 2006.
• T. King, "Negative differential resistance (NDR) elements and memory device using the same," U.S. Patent 7,098,472. Aug. 2006.
• Q. Ji, K. Standiford, T. King, and K. Leung, "Ion beam extractor with counterbore," U.S. Patent 7,084,407. Aug. 2006.
• T. King, "Methods of testing/stressing a charge trapping device," U.S. Patent 7,060,524. June 2006.
• T. King and D. K. Y. Liu, "Charge trapping device," U.S. Patent 7,067,873. June 2006.
• T. King and D. K. Y. Liu, "Charge trapping device," U.S. Patent Application. May 2006.
• T. King, "Two terminal silicon based negative differential resistance device," U.S. Patent 7,016,224. March 2006.
• T. King, "Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)," U.S. Patent 7,012,833. March 2006.
• T. King, "Enhanced read and write methods for negative differential resistance (NDR) based memory device," U.S. Patent 7,012,842. March 2006.
• T. King, "Charge trapping device and method of forming the same," U.S. Patent 7,015,536. March 2006.
• T. King, "N-channel pull-up element and logic circuit," U.S. Patent 7,005,711. Feb. 2006.
• T. King, "Method of making memory cell utilizing negative differential resistance devices," U.S. Patent 6,990,016. Jan. 2006.
• T. King, "Process for controlling performance characteristics of a negative differential resistance (NDR) device," U.S. Patent 6,979,580. Dec. 2005.
• T. King, "Method of forming a negative differential resistance device," U.S. Patent 6,980,467. Dec. 2005.
• T. King and D. K. Y. Liu, "CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same," U.S. Patent 6,972,465. Dec. 2005.
• T. King and D. K. Y. Liu, "Variable threshold semiconductor device and method of operating same," U.S. Patent 6,969,894. Nov. 2005.
• T. King, "Charge trapping pull up element," U.S. Patent 6,956,262. Oct. 2005.
• T. King, "Negative differential resistance pull up element for DRAM," U.S. Patent Application. Aug. 2005.
• T. King, "Negative differential resistance load element," U.S. Patent 6,933,548. Aug. 2005.
• T. King, "Negative differential resistance (NDR) based memory device with reduced body effects," U.S. Patent 6,912,151. June 2005.
• K. Shin and T. King, "Complementary field-effect transistors having enhanced performance with a single capping layer," U.S. Patent Application. June 2005.
• M. She and T. King, "Two bit/four bit SONOS flash memory cell," U.S. Patent Application. May 2005.
• T. King, "Negative differential resistance pull up element," U.S. Patent 6,894,327. May 2005.
• T. King, "Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects," U.S. Patent 6,864,104. March 2005.
• T. King, "Negative differential resistance (NDR) memory cell with reduced soft error rate," U.S. Patent 6,861,707. March 2005.
• T. King, "Negative differential resistance (NDR) memory device with reduced soft error rate," U.S. Patent 6,853,035. Feb. 2005.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," U.S. Patent 6,855,994. Feb. 2005.
• T. King, "Charge trapping device and method of forming the same," U.S. Patent 6,849,483. Feb. 2005.
• T. King, "Enhanced read and write methods for negative differential resistance (NDR) based memory device," U.S. Patent 6,847,562. Jan. 2005.
• T. King, "Negative differential resistance (NDR) memory device with reduced soft error rate," U.S. Patent Application. Dec. 2004.
• T. King, "Method of making adaptive negatie differential resistance device," U.S. Patent Application. Nov. 2004.
• M. She and T. King, "Flash memory devices using large electron affinity material for charge trapping," U.S. Patent Application. Nov. 2004.
• T. King, "Adaptive negative differential resistance device," U.S. Patent 6,812,084. Nov. 2004.
• T. King, "Methods of testing/stressing a charge trapping device," U.S. Patent 6,806,117. Oct. 2004.
• T. King, "Negative differential resistance (NDR) elements and memory device using the same," U.S. Patent 6,795,337. Sep. 2004.
• I. Polishchuk, P. Ranade, T. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," U.S. Patent 6,794,234. Sep. 2004.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," U.S. Patent 6,753,229. June 2004.
• T. King, "Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET," U.S. Patent 6,754,104. June 2004.
• T. King, "Negative differential resistance (NDR) element and memory with reduced soft error rate," U.S. Patent 6,727,548. April 2004.
• T. King, "Memory cell using negative differential resistance field effect transistors," U.S. Patent 6,724,655. April 2004.
• T. King, "Field effect transistor pull-up/load element," U.S. Patent 6,724,024. April 2004.
• T. King and D. K. Y. Liu, "Charge trapping device and method for implementing a transistor having a configurable threshold," U.S. Patent 6,700,115. March 2004.
• T. King and D. K. Y. Liu, "Negative differential resistance (NDR) device and method of operating same," U.S. Patent 6,686,631. Feb. 2004.
• T. King, "Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode," U.S. Patent 6,686,267. Feb. 2004.
• T. King and D. K. Y. Liu, "Method for configuring a device to include a negative differential resistance (NDR) characteristic," U.S. Patent 6,693,027. Feb. 2004.
• T. King and D. K. Y. Liu, "Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process," U.S. Patent 6,680,245. Jan. 2004.
• T. King, "Method of operating a dual mode FET & logic circuit having negative differential resistance mode," U.S. Patent 6,664,601. Dec. 2003.
• T. King, "Charge pump for negative differential resistance transistor," U.S. Patent 6,594,193. July 2003.
• T. King and D. K. Y. Liu, "CMOS compatible process for making a tunable negative differential resistance (NDR) device," U.S. Patent 6,596,617. July 2003.
• T. King, "Negative differential resistance field effect transistor (NDR-FET) and circuits using the same," U.S. Patent 6,559,470. May 2003.
• T. King, "Negative differential resistance (NDR) element and memory with reduced soft error rate," U.S. Patent 6,567,292. May 2003.
• T. King, "Dual mode FET & logic circuit having negative differential resistance mode," U.S. Patent 6,518,589. Feb. 2003.
• T. King and D. K. Y. Liu, "CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same," U.S. Patent 6,512,274. Jan. 2003.
• T. King and D. K. Y. Liu, "Charge trapping device and method for implementing a transistor having a negative differential resistance mode," U.S. Patent 6,479,862. Nov. 2002.
• A. Franke, R. T. Howe, and T. King, "Polycrystalline silicon-germanium films for micro-electromechanical systems application," U.S. Patent 6,448,622. Sep. 2002.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," Aug. 2002.
• C. Hu, T. King, V. Subramanian, L. Chang, X. Huang, Y. Choi, J. T. Kedzierski, N. Lindert, J. Bokor, and W. Lee, "FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture," U.S. Patent 6,413,802. July 2002.
• R. T. Howe, A. Franke, and T. King, "Polycrystalline silicon germanium films for forming micro-electromechanical systems," U.S. Patent 6,210,988. April 2001.
• T. King and J. H. Ho, "Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates," U.S. Patent 5,893,949. April 1999.
• T. King and J. H. Ho, "Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates," U.S. Patent 5,707,744. Jan. 1998.
• T. King and M. G. Hack, "Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions," U.S. Patent 5,401,982. March 1995.
• K. C. Saraswat and T. King, "Low temperature germanium-silicon on insulator thin-film transistor," U.S. Patent 5,250,818. Oct. 1993.