Electrical Engineering and Computer Sciences

Electrical Engineering and Computer Sciences

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UC Berkeley

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Faculty Publications - Tsu-Jae King Liu

Book chapters or sections

  • T. King Liu and L. Chang, "Transistor scaling to the limit," in Into the Nano Era: Moore's Law Beyond Planar Silicon CMOS, H. R. Huff, Ed., Springer Series in Materials Science, Vol. 106, Berlin, Germany: Springer-Verlag, 2008, pp. 191-223.
  • A. Carlson and T. King Liu, "Negative and iterated spacer lithography processes for low variability and ultra-dense integration," in Optical Microlithography XXI, H. J. Levinson and M. V. Dusa, Eds., SPIE -- Society of Photo-Optical Instrumentation Engineers, Vol. 6924, Bellingham, WA: SPIE -- The International Society for Optical Engineering, 2008, pp. 69240B-1-9.
  • K. Patel, T. King Liu, and C. J. Spanos, "Impact of gate line edge roughness on double-gate FinFET performance variability," in Design for Manufacturability through Design-Process Integration II, V. K. Singh and M. L. Rieger, Eds., Proceedings of SPIE, Vol. 6925, Bellingham, WA: SPIE -- Society of Photo-Optical Instrumentation Engineers, 2008, pp. 1I-1-10.
  • B. C. Y. Lin, T. King Liu, and R. S. Muller, "Poly-SiGe MEMS actuators for adaptive optics," in MEMS/MOEMS Components and Their Applications IIII, S. S. Olivier, S. A. Tadigadapa, and A. K. Henning, Eds., Proceedings of SPIE, Vol. 6113, Bellingham, WA: SPIE -- Society of Photo-Optical Instrumentation Engineers, 2006, pp. 61130S-1-7.

Articles in journals or magazines

Articles in conference proceedings

  • H. Kam, E. Alon, and T. King Liu, "A predictive contact reliability model for MEM logic switches," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 16.4.1 -16.4.4. [abstract]
  • T. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott, and E. Alon, "Prospects for MEM logic switch technology," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 18.3.1 -18.3.4. [abstract]
  • H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T. King Liu, E. Alon, V. Stojanovic, and D. Markovic, "Analysis and demonstration of MEM-relay power gating," in Custom Integrated Circuits Conference (CICC), 2010 IEEE, 2010, pp. 1 -4. [abstract]
  • W. Kwon and T. King Liu, "Compact NAND Flash Memory Cell Design Utilizing Backside Charge Storage," in 2010 IEEE Silicon Nanoelectronics Workshop, 2010. [abstract]
  • F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. King Liu, D. Markovic, V. Stojanovic, and E. Alon, "Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 150 -151.
  • H. Kam, V. Pott, R. Nathanael, J. Jeon, E. Alon, and T. King Liu, "Design and reliability of a micro-relay technology for zero-standby-power digital logic applications," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1 -4.
  • W. Kwon and T. King Liu, "A Highly Scalable 4FH<sub>2</sub> DRAM Cell Utilizing a Doubly Gated Vertical Channel," in International Conference on Solid State Devices and Materials, THE JAPAN SOCIETY OF APPLIED PHYSICS, 2009. [abstract]
  • N. Xu, X. Sun, L. Wang, A. R. Neureuther, and T. King Liu, "Predictive compact modeling for strain effects in nanoscale transistors," in 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2009), 2009. [abstract]
  • P. Kalra, P. Majhi, H. H. Tseng, R. Jammy, and T. King Liu, "Optimization of flash annealing parameters to achieve ultra-shallow junctions for sub-45nm CMOS," in Doping Engineering for Front-End Processing: Proc. 2008 MRS Spring Meeting, B. J. Pawlak, M. L. Pelaz, M. Law, and K. Suguro, Eds., MRS Proceedings, Vol. 1070, Warrendale, PA: Materials Research Society, 2008, pp. 6 pg.
  • H. Kam, T. King Liu, E. Alon, and M. Horowitz, "Circuit-Driven Requirements for CMOS-Replacement Devices," in IEEE International Electron Devices Meeting, 2008.
  • P. Kalra, P. Majhi, H. H. Tseng, R. Jammy, and T. King Liu, "Infusion doping for sub-45nm CMOS technology nodes," in Proc. 17th Intl. Conf. on Ion Implantation Technology, E. G. Seebauer, S. B. Felch, A. Jain, and Y. V. Kondratenko, Eds., AIP Conference Proceedings: Materials Physics and Applications, Vol. 1066, Warrendale, PA: American Institute of Physics, 2008.
  • P. Kalra, P. Majhi, H. H. Tseng, L. Larson, R. jammy, and T. King Liu, "USJ process challenges for sub-45nm CMOS (Invited)," in Proc. 17th Intl. Conf. on Ion Implantation Technology, E. G. Seebauer, S. B. Felch, A. Jain, and Y. V. Kondratenko, Eds., AIP Conference Proceedings: Materials Physics and Applications, Vol. 1066, Melville, NY: American Institute of Physics, 2008, pp. 55-62.
  • F. Chen, H. Kam, D. Markovic, T. King Liu, V. Stojanovic, and E. Alon, "Integrated Circuit Design with NEM Relays," in IEEE/ACM International Conference on Computer-Aided Design, 2008.
  • A. Carlson, Z. Guo, L. T. Pang, T. King Liu, and B. Nikolic, "Compensation of systematic variations through optimal biasing of SRAM wordlines," in Proc. 2008 Custom Integrated Circuits Conf. (CICC '08), Piscataway, NJ: IEEE Press, 2008.
  • C. Shin, A. Carlson, X. sun, K. Jeon, and T. King Liu, "Tri-gate bulk MOSFET design for improved robustness to random dopant fluctuations," in Proc. IEEE 2008 Silicon Nanoelectronics Workshop, Piscataway, NJ: IEEE Press, 2008.
  • A. Carlson, X. Sun, C. Shin, and T. King Liu, "SRAM yield and performance enhancements with tri-gate bulk MOSFETs," in Proc. IEEE 2008 Silicon Nanoelectronics Workshop, Piscataway, NJ: IEEE Press, 2008.
  • A. Padilla, S. Lee, D. Carlton, and T. King Liu, "Enhanced endurace of dual-bit SONOS NVM cells using the GIDL read method," in 2008 Symp. on VLSI Technology Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2008, pp. 142-143.
  • Z. Guo, A. Carlson, L. Pang, K. Duong, T. King Liu, and B. Nikolic, "Large-scale read/write margin measurement in 45nm CMOS SRAM arrays," in Proc. 2008 IEEE Symp. on VLSI Circuits, Piscataway, NJ: IEEE Press, 2008, pp. 42-43.
  • H. H. Tseng, P. Kalra, J. Oh, P. Majhi, T. King Liu, and R. Jammy, "The Challenges and Progress of USJ Formation and Process Integration for 32nm Technology and Beyond (Keynote)," in Proc. 2008 Intl. Workshop on Junction Technology (IWJT '08), Piscataway, NJ: IEEE Press, 2008, pp. 3-6.
  • P. Kalra, P. Majhi, D. Heh, G. Bersuker, C. Young, N. Vora, R. Harris, P. Kirsch, R. choi, M. Chang, J. Lee, H. Hwang, H. H. Tseng, R. Jimmy, and T. King Liu, "Impact of flash annealing on performance and reliability of high-k/metal-gate MOSFETs for sub-45nm CMOS," in 53rd IEEE Intl. Electon Devices Meeting (IEDM 2007) Technical Digest, Piscataway, NJ: IEEE Press, 2007, pp. 353-356.
  • W. Y. Choi, H. Kam, D. Lee, J. Lai, and T. King Liu, "Compact nano-electro-mechanical non-volatile memory (NEMory) for 3D integration," in 53rd IEEE Intl. Electon Devices Meeting (IEDM 2007) Technical Digest, Piscataway, NJ: IEEE Press, 2007, pp. 603-606.
  • C. H. Hsu, W. Xiong, C. T. Lin, Y. T. Huang, M. Ma, C. R. Cleavelin, P. Patruno, M. kennard, I. Cayrefourcq, K. Shin, and T. King Liu, "Multi-gate MOSFETs with dual contact etch stop liner stressors on tensile metal gate and strained silicon on insulator (sSOI)," in Proc. 2007 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '07), Piscataway, NJ: IEEE Press, 2007, pp. 2 pg.
  • A. Padilla and T. King Liu, "Dual-bit SONOS FinFET non-volatile memory cell and new method of charge detection," in Proc. 2007 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '07), Piscataway, NJ: IEEE Press, 2007, pp. 2 pg.
  • D. Lee, X. Sun, E. Quevy, R. T. Howe, and T. King Liu, "WetFET--A novel fluidic gate-dielectric transistor for sensor applications (Best Student Paper Award)," in Proc. 2007 Intl. Symp. on VLSI Technology, Systems and Applications (VLSI-TSA '07), Piscataway, NJ: IEEE Press, 2007, pp. 2 pg.
  • K. Shin, S. Balasubramanian, X. Sun, and T. King Liu, "Strain engineering and body biasing for optimization of sub-45nm CMOS performance (Invited)," in Proc. MRS 2006 Spring Meeting, Warrendale, PA: Materials Research Society, 2006.
  • V. Varadarajan, Y. Yasuda, S. Balasubramanian, and T. King Liu, "WireFET technology for 3-D integrated circuits," in 52nd Intl. Electron Devices Meeting (IEDM 2006) Technical Digest, Piscataway, NJ: IEEE Press, 2006, pp. 4 pg.
  • H. Takeuchi, K. Shiraishi, and T. King Liu, "Role of oxygen states in high-k gate stack engineering (Invited)," in Proc. 8th Intl. Conf. on Solid-State and Integrated Circuit Technology (ICSICT-2006), T. A. Tang, G. P. Ru, and Y. L. Jiang, Eds., Piscataway, NJ: IEEE Press, 2006, pp. 388-391.
  • K. Shiraishi, H. Takeuchi, Y. Akasaka, T. Nakayama, S. Miyazaki, T. Nakaoka, A. Ohta, H. Watanabe, N. Umezawa, K. Ohmori, P. Ahmet, K. Toii, T. Chikyow, Y. Nara, T. King Liu, H. Iwai, and K. Yamada, "Physics of interfaces between gate electrodes and high-k dielectrics (Invited)," in Proc. 8th Intl. Conf. on Solid-State and Integrated Circuit Technology (ICSICT-2006), T. A. Tang, G. P. Ru, and Y. L. Jiang, Eds., Piscataway, NJ: IEEE Press, 2006, pp. 384-387.
  • A. Carlson, Z. Guo, S. Balasubramanian, L. T. Pang, T. King Liu, and B. Nikolic, "FinFET SRAM with enhanced read/write margins," in Proc. 2006 IEEE Intl. SOI Conf. (SOI '06), Piscataway, NJ: IEEE Press, 2006, pp. 105-106.
  • K. Shiraishi, Y. Akasaka, N. Umezawa, Y. Nara, K. Yamada, H. Takeuchi, H. Watanabe, T. Chikyow, and T. King Liu, "Theory of Fermi level pinning of high-k dielectrics," in Proc. 2006 Intl. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD '06), Piscataway, NJ: IEEE Press, 2006.
  • G. Liu, T. King Liu, and A. Niknejad, "A 1.2V, 2.4GHz fully integrated linear CMOS power amplifier with efficiency enhancement," in Proc. 2006 IEEE Custom Integrated Circuits Conf. (CICC '06), Piscataway, NJ: IEEE Press, 2006, pp. 141-144.
  • Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED '05, Piscataway, NJ: IEEE, 2005, pp. 2-7.
  • P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. King Liu, "FinFET SONOS flash memory for embedded applications," in 2003 Intl. Electron Devices Meeting (IEDM '03). Technical Digest, Piscataway, NJ: IEEE Press, 2003, pp. 609-612.
  • M. She, H. Takeuchi, and T. King Liu, "Improved SONOS-type flash memory using HfO2 as trapping layer," in 19th IEEE Non-Volatile Semiconductor Memory Workshop Digest, Piscataway, NJ: IEEE, 2003, pp. 53-55.
  • B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
  • B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, T. King Liu, J. Bokor, M. Lin, and D. Kyser, "FinFET scaling: Towards 10nm gate length," in IEDM '02 Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
  • J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. King Liu, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," in 2000 Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2000, pp. 57-60.
  • S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W. Sigmon, Y. J. Tung, and T. King Liu, "Polysilicon thin film transistors fabricated at 100°C on a flexible plastic substrate," in International Electron Devices Meeting 1998 Technical Digest, Piscataway, NJ: IEEE, 1998, pp. 257-260.

Technical Reports

Patents

Ph.D. Theses