Faculty Publications - Kurt Keutzer

Books

• M. Gries and K. W. Keutzer, Eds., Building ASIPs: The MESCAL Methodology, New York: Springer, 2005.
• P. Chen, D. A. Kirkpatrick, and K. W. Keutzer, Static Crosstalk-Noise Analysis: For Deep Sub-Micron Digital Designs, Norwell, MA: Kluwer Academic Publishers, 2004.
• D. Chinnery and K. Keutzer, Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Boston, MA: Kluwer Academic Publishers, 2002.
• S. Devadas, A. Ghosh, and K. W. Keutzer, Logic Synthesis, McGraw-Hill Series on Computer Engineering, New York: McGraw-Hill, 1994.

Articles in journals or magazines

• D. I. August, K. Keutzer, S. Malik, and A. R. Newton, "A disciplined approach to the development of platform architectures," Microelectronics J., vol. 33, no. 11, pp. 881-890, Nov. 2002.
• R. E. Bryant, K. T. Cheng, A. B. Kahng, K. Keutzer, W. Maly, A. R. Newton, L. Pileggi, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Invited Paper: Limitations and challenges of computer aided design technology for CMOS VLSI," Proc. IEEE, vol. 89, no. 3, pp. 341-365, March 2001.
• K. Keutzer, S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
• K. Keutzer, S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Invited Paper: System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
• D. August, K. Keutzer, S. Malik, and A. R. Newton, "Programmable ASICs to reduce costs," EE Times, Nov. 2000.
• S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang, "Storage assignment to decrease code size," SIGPLAN Notices, vol. 30, no. 6, pp. 186-195, June 1995.
• L. Lavagno, K. Keutzer, and A. L. Sangiovanni-Vincentelli, "Synthesis of hazard-free asynchronous circuits with bounded wire delays," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 1, pp. 61-86, Jan. 1995.

Articles in conference proceedings

• J. Chong, N. R. Satish, B. C. Catanzaro, K. Ravindran, and K. Keutzer, "Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling," in ICME, 2007.
• N. R. Satish, K. Ravindran, and K. Keutzer, "A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors," in 10th Conference of Design, Automation and Test in Europe (DATE), 2007, pp. 57-62.
• Y. Jin, N. R. Satish, K. Ravindran, and K. Keutzer, "An Automated Exploration Framework for FPGA-based Soft Multiprocessor Systems," in Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES), ACM Press, 2005, pp. 273-278.
• K. Ravindran, N. R. Satish, Y. Jin, and K. Keutzer, "An FPGA-based Soft Multiprocessor for IPv4 Packet Forwarding," in 15th International Conferenece on Field Programmable Logic and Applications (FPL), 2005, pp. 487-492.
• K. Keutzer, S. Malik, and A. R. Newton, "From ASIC to ASIP: The next design discontinuity," in Proc. 2002 IEEE Conf. on Computer Design, Los Alamitos, CA: IEEE Computer Society Press, 2002, pp. 84-90.
• K. Keutzer and A. R. Newton, "Plenary Talk: The MARCO/DARPA Gigascale Silicon Research Center," in Proc. 1999 Intl. Conf. on Computer Design (ICCD '99), Los Alamitos, CA: IEEE Computer Society Press, 1999, pp. 14-19.
• D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in 1998 IEEE/ACM Intl. Conf. on Computer-Aided Design. Digest of Technical Papers, New York, NY: ACM, 1998, pp. 203-11.
• K. Keutzer, A. R. Newton, and N. V. Shenoy, "The future of logic synthesis and physical design in deep-submicron process geometries," in Proc. 1997 Intl. Symp. on Physical Design, New York, NY: ACM, Inc., 1997, pp. 218-224.
• A. Ghosh, S. Devadas, K. Keutzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," in Proc. 29th ACM/IEEE Conf. on Design Automation, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 253-259.
• K. Keutzer, "DAGON: Technology binding and local optimization by DAG matching," in Proc. 24th ACM/IEEE Conf. on Design Automation, Piscataway, NJ: IEEE, 1987, pp. 341-347.

Technical Reports

• J. Chong, Y. Yi, A. Faria, N. R. Satish, and K. Keutzer, "Data-Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-69, May 2008.
• N. R. Satish, K. Ravindran, and K. Keutzer, "Scheduling Task Dependence Graphs with Variable Task Execution Times onto Heterogeneous Multiprocessors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-42, April 2008.
• K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-23, March 2008.
• M. Murphy, K. Keutzer, L. Oliker, C. Rowen, and J. Shalf, "Evaluating Architectures for Application-Specific Parallel Scientific Computing Systems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-13, Feb. 2008.
• B. C. Catanzaro, N. Sundaram, and K. Keutzer, "Fast Support Vector Machine Training and Classification on Graphics Processors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-11, Feb. 2008.
• K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The Landscape of Parallel Computing Research: A View from Berkeley," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-183, Dec. 2006.
• A. C. Mihal, C. Sauer, and K. Keutzer, "Designing a Sub-RISC Multi-Gigabit Regular Expression Processor," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-119, Sep. 2006.
• C. Sauer, M. Gries, C. Kulkarni, and K. Keutzer, "Performance Analysis of the Peripheral-Processor Interaction in Embedded Systems," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/26, 2003.
• J. Weber, M. W. Moskewicz, M. Low, and K. Keutzer, "Multi-View Operation-level DesignSupporting the Design of Irregular ASIPs," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M03/12, 2003.
• N. Shah, W. Plishker, and K. Keutzer, "A Programming Model for Network Processors," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M02/35, 2002.
• P. Chong, M. Prasad, and K. Keutzer, "Why Is ATPG Easy?," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/9, 1999.
• K. Keutzer, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Synthesis for Testability Techniques for Asynchronous Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/77, 1991.
• L. Lavagno, K. Keutzer, and A. L. Sangiovanni-Vincentelli, "Synthesis of Verifiably Hazard-Free Asynchronous Control Circuits," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/99, 1990.