Faculty Publications - Chenming Hu

Books

• Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide, Boston, MA: Kluwer Academic Publishers, 1999.
• C. Hu, Ed., Nonvolatile Semiconductor Memories: Technologies, Design, and Applications, IEEE Press Selected Reprint Series, New York: Institute of Electrical and Electronics Engineers, 1991.
• C. Hu and R. M. White, Solar Cells: From Basics to Advanced Systems, McGraw-Hill Series in Electrical Engineering: Power and Energy, New York: McGraw-Hill, 1983.

Articles in journals or magazines

• M. V. Dunga, C. Lin, X. Xi, D. Lu, A. Niknejad, and C. Hu, "Modeling Advanced FET Technology in a Compact Model," IEEE Transactions on Electronic Devices, vol. 53, pp. 1971-1978, Sep. 2006.
• S. Lam, H. Wan, P. Su, P. Wyatt, C. Chen, A. Niknejad, C. Hu, P. Ko, and M. Chan, "RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology," IEEE Electron Device Letters, vol. 24, pp. 251-253, April 2003.
• P. Su, S. Fung, P. Wyatt, W. Hui, A. Niknejad, M. Chan, and C. Hu, "On the body-source built-in potential lowering of SOI MOSFETs," IEEE Electron Device Letters, vol. 24, pp. 90-92, Feb. 2003.
• C. Kuo, T. King Liu, and C. Hu, "A capacitorless double-gate DRAM cell," IEEE Electron Device Letters, vol. 23, no. 6, pp. 345-347, June 2002.
• Y. Choi, T. King Liu, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, March 2002.
• Y. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. King Liu, J. Bokor, and C. Hu, "Paul Rappaport Award for 2002: Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 279-286, Feb. 2002.
• D. Hisamoto, W. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. King Liu, J. Bokor, and C. Hu, "FinFET--A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
• Y. Shih, G. Zhang, C. Hu, and W. G. Oldham, "Thin dielectric degradation during silicon selective epitaxial growth process," Applied Physics Letters, vol. 67, no. 14, pp. 2040-2042, Oct. 1995.
• K. F. Schuegraf and C. Hu, "Reliability of thin SiO2," Semiconductor Science and Technology, vol. 9, no. 5, pp. 989-1004, May 1994.
• Y. Fong, G. C. Liang, T. Van Duzer, and C. Hu, "Channel width effect on MOSFET breakdown," IEEE Trans. Electron Devices, vol. 39, no. 5, pp. 1265-1267, May 1992.
• C. Hu, "IC reliability simulation," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 241-246, March 1992.
• C. Hu, S. Tam, F. Hsu, P. Ko, T. Chan, and K. W. Terrill, "Hot-electron-induced MOSFET degradation--Model, monitor, improvement," IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 375-385, Feb. 1985.
• J. R. Whinnery, C. Hu, and Y. S. Kwon, "Liquid-crystal waveguides for integrated optics," IEEE J. Quantum Electronics, vol. 13, no. 4, pt. 1, pp. 262-267, April 1977.
• C. Hu and J. R. Whinnery, "Losses of a nematic liquid-crystal optical waveguide," J. Optical Society of America, vol. 64, no. 11, pp. 1424-1432, Nov. 1974.
• C. Hu and J. R. Whinnery, "Field-realigned nematic-liquid-crystal optical waveguides," IEEE J. Quantum Electronics, vol. 10, no. 7, pp. 556-562, July 1974.
• C. Hu, J. R. Whinnery, and N. M. Amer, "Optical deflection in thin-film nematic-liquid-crystal waveguides," IEEE J. Quantum Electronics, vol. 10, no. 2, pt. 1, pp. 218-222, Feb. 1974.
• C. Hu, J. R. Whinnery, and N. Amer, "Liquid crystals in integrated optics," IEEE J. Quantum Electronics, vol. 9, no. 6, pp. 684-685, June 1973.
• C. Hu and J. R. Whinnery, "New thermooptical measurement method and a comparison with other methods," Applied Optics, vol. 12, no. 1, pp. 72-79, Jan. 1973.
• M. S. Chang, P. Burlamacchi, C. Hu, and J. R. Whinnery, "Light amplification in a thin film," Applied Physics Letters, vol. 20, no. 8, pp. 313-314, April 1972.

Articles in conference proceedings

• A. Niknejad, M. V. Dunga, B. Heydari, H. Wan, C. Lin, S. Emami Neyestanak, C. Doan, X. Xi, J. He, and C. Hu, "Challenges in compact modeling for RF and microwave applications," in Workshop on Compact Modeling, 2005, pp. N/A.
• J. He, J. Xi, M. Chan, H. Wan, M. V. Dunga, B. Heydari, A. Niknejad, and C. Hu, "Charge-based core and the model architecture of BSIM5," in Quality of Electronic Design, 2005, pp. 96-101.
• A. Niknejad, C. Doan, S. Emami Neyestanak, M. V. Dunga, X. Xi, J. He, R. W. Brodersen, and C. Hu, "Next generation CMOS compact mofels for RF and microwave applications (Invited)," in RFIC Digest of Papers, 2005, pp. 141-144.
• X. Xi, J. He, M. V. Dunga, C. Lin, B. Heydari, H. Wan, M. Chan, A. Niknejad, and C. Hu, "The next generation BSIM for sun-100nm mixed-signal circuit simulation," in Proceedings of CICC, 2004, pp. 13-16.
• M. Chan, C. Lin, J. He, Y. Taur, A. Niknejad, and C. Hu, "A framework for modeling double-Gate MOSFETs," in Workshop on Compact Modeling, 2003, pp. N/A.
• J. He, X. Xi, M. Chan, A. Niknejad, and C. Hu, "An advanced surface-potential-plus MOSFET model," in Workshop on Compact Modeling, 2003, pp. N/A.
• M. V. Dunga, X. Xi, J. He, I. Polishchuk, Q. Lu, M. Chan, A. Niknejad, and C. Hu, "Modeling of direct tunneling current in multi-layer gate stacks," in Workshop on Compact Modeling, 2003, pp. N/A.
• A. Niknejad, M. Chan, C. Hu, X. Xi, J. He, P. Su, Y. Cao, H. Wan, M. V. Dunga, C. Doan, S. Emami Neyestanak, and C. Lin, "Compact modeling for RF and microwave applications (Invited)," in Workshop on Compact Modeling, 2003, pp. N/A.
• C. Lin, J. He, X. Xi, H. Kam, A. Niknejad, M. Chan, and C. Hu, "The impact of scaling on volume inversion in symmetric double-gate MOSFETs," in Semiconductor Device Research Symposium, 2003, pp. 148-149.
• C. Lin, P. Su, Y. Taur, X. Xi, J. He, A. Niknejad, M. Chan, and C. Hu, "Circuit performance of double-gate SOI CMOS," in Semiconductor Device Research Symposium, 2003, pp. 266-267.
• P. Su, S. Fung, P. Wyatt, H. Wan, M. Chan, A. Niknejad, and C. Hu, "A unified model for partial-depletion and full depletion SOI circuit designs: Using BSIMPD as a foundation," in Proceedings of CICC, 2003, pp. N/A.
• P. Su, S. Fung, H. Wan, A. Niknejad, M. Chan, and C. Hu, "An impact ionization model for SOI circuit simulation," in IEEE International SOI Conference, 2002, pp. 201-202.
• B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
• J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. King Liu, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," in 2000 Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2000, pp. 57-60.

Technical Reports

• W. Liu, X. Jin, K. Kao, and C. Hu, "BSIM 4.1.0 MOSFET Model-User's Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/48, 2000.
• W. Liu, K. Cao, X. Jin, and C. Hu, "BSIM 4.0.0 Technical Notes," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/39, 2000.
• W. Liu, X. Jin, K. Cao, and C. Hu, "BSIM 4.0.0 MOSFET Model User's Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M00/38, 2000.
• C. Hu, J. Feng, W. Liu, S. Fung, P. Su, and S. Tang, "BSIM01 v2.0 MOSFET Model - User's Manual for BSIMFD2.0," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/44, 1999.
• C. Hu, J. Feng, W. Liu, S. Fung, P. Su, and S. Tang, "BSIMS01 v2.0 MOSFET Model - User's Manual for BSIM002.0," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/43, 1999.
• W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, "BSIM3v3.2.1 MOSFET Model Users' Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/19, 1999.
• W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, "BSIM3v3.2.2 MOSFET Model Users' Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M99/18, 1999.
• W. Liu, X. Jin, J. Chen, M. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu, "BSIM 3v3.2 MOSFET Model Users' Manual," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/51, 1998.
• W. Liu, X. Jin, Y. King, and C. Hu, "An Accurate MOSFET Intrinsic Capacitance Model Considering Quantum Mechanic Effect for BSIM 3v3.2," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M98/47, 1998.
• Y. Cheng, M. Chan, K. Hui, M. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu, P. Ko, and C. Hu, "BSIM 3v3 Manual (Final Version)," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M97/2, 1997.
• J. Huang, Z. Liu, M. Jeng, P. Ko, and C. Hu, "A Robust Physical and Predictive Model for Deep-Submicrometer MOS Circuit Simulation," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/57, 1993.
• J. Huang, Z. Liu, M. Jeng, P. Ko, and C. Hu, "A Physical Model for MOSFET Output Resistance," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M93/56, 1993.
• R. Tu, E. Rosenbaum, C. Li, W. Chan, P. Lee, B. Liew, J. Burnett, P. Ko, and C. Hu, "BERT - Berkeley Reliability Tools," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M91/107, 1991.
• E. Rosenbaum, P. Lee, R. Moazzami, P. Ko, and C. Hu, "BERT - Circuit Oxide Reliability Simulator (CORS)," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/4, 1990.
• B. Liew, P. Fang, N. W. Cheung, and C. Hu, "BERT - Circuit Electromigration Simulator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/3, 1990.
• P. Lee, M. Kuo, P. Ko, and C. Hu, "BERT - Circuit Aging Simulator (CAS)," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M90/2, 1990.
• H. Park, P. Ko, and C. Hu, "SPICE3 Implementation of a Non-Quasi-Static MOSFET Model with Level-2 DC Model," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M89/70, 1989.
• M. Kuo, K. Seki, P. Lee, P. Ko, and C. Hu, "Implementation of the BSIM Substrate Current and Degradation Models in SCALP," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/39, 1987.
• M. Jeng, P. Lee, M. Kuo, P. Ko, and C. Hu, "Theory, Algorithms, and User's Guide for BSIM and SCALP," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/35, 1987.
• P. Lee, M. Kuo, M. Maghsoodnia, P. Ko, and C. Hu, "BSIM - Substrate Current Modeling Appendix C: Implementation of the BSIM Substrate Current and Degradation Models in SCALP," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M87/8, 1987.
• P. Lee, P. Ko, and C. Hu, "BSIM - Substrate Current Modeling Appendix C: SPICE Implementation of the BSIM Substrate Current and Degradation Models," EECS Department, University of California, Berkeley, Tech. Rep. UCB/ERL M86/64, 1986.

Patents

• K. Yang, Y. Chang, Y. Chu, H. Chen, F. Yang, and C. Hu, "High performance tunneling-biased MOSFET and a process for its manufacture," U.S. Patent 7,187,000. March 2007.
• F. Yang, Y. Yeo, H. Tseng, and C. Hu, "Self-aligned contact for silicon-on-insulator devices," U.S. Patent 7,173,305. Feb. 2007.
• Y. Yeo, F. Yang, and C. Hu, "Multiple-gate transistors formed on bulk substrates," U.S. Patent 7,172,943. Feb. 2007.
• F. Yang, Y. Yeo, and C. Hu, "Methods and structures for planar and multiple-gate transistors formed on SOI," U.S. Patent 7,180,134. Feb. 2007.
• H. Lee, C. Huang, C. Wang, F. Yang, and C. Hu, "Method for dicing semiconductor wafers," U.S. Patent 7,183,137. Feb. 2007.
• Y. Yeo, W. Lee, C. Ko, C. Ge, C. Lin, and C. Hu, "Heterostructure resistor and method of forming the same," U.S. Patent 7,183,593. Feb. 2007.
• Y. Yeo, H. Chen, F. Yang, and C. Hu, "Gate electrode for a semiconductor fin device," U.S. Patent 7,176,092. Feb. 2007.
• Y. Yeo and C. Hu, "Strained silicon-on-insulator transistors with mesa isolation," U.S. Patent 7,157,774. Jan. 2007.
• C. Hu and G. Zhang, "Hybrid fractional-bit systems," U.S. Patent 7,167,109. Jan. 2007.
• F. Yang, H. Chen, Y. Yeo, C. H. Diaz, and C. Hu, "Silicon-on-insulator ULSI devices with multiple silicon film thicknesses," U.S. Patent 7,141,459. Nov. 2006.
• I. Polishchuk, P. Ranade, T. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," U.S. Patent 7,141,858. Nov. 2006.
• H. Chen, F. Chen, Y. Chan, K. Yang, F. Yang, and C. Hu, "Necked FinFET device," U.S. Patent Application. Oct. 2006.
• H. Chen, F. Chen, Y. Chan, K. Yang, F. Yang, and C. Hu, "Method of fabricating a necked FINFET device," U.S. Patent 7,122,412. Oct. 2006.
• C. Su, P. Tsai, H. Lee, C. Huang, S. Y. Hou, S. P. Jeng, H. Tsai, and C. Hu, "Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling," U.S. Patent 7,126,225. Oct. 2006.
• C. Ko, W. Lee, Y. Yeo, C. Lin, and C. Hu, "Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit," U.S. Patent 7,112,495. Sep. 2006.
• C. Ko, Y. Yeo, C. Lin, and C. Hu, "Strained channel complementary field-effect transistors and methods of manufacture," U.S. Patent 7,101,742. Sep. 2006.
• C. Lin, W. Lee, Y. Yeo, C. Lin, and C. Hu, "Method for forming a device having multiple silicide types," U.S. Patent 7,112,483. Sep. 2006.
• C. Yu, H. Tseng, C. Hu, and C. Wang, "Copper wiring with high temperature superconductor (HTS) layer," U.S. Patent 7,105,928. Sep. 2006.
• Y. Yeo, F. Yang, and C. Hu, "Contacts to semiconductor fin devices," U.S. Patent 7,105,894. Sep. 2006.
• C. Ke, W. Lee, and C. Hu, "Thermal anneal process for strained-Si devices," U.S. Patent 7,098,119. Aug. 2006.
• C. Lin, W. Lee, Y. Yeo, C. Lin, and C. Hu, "A method for forming a device having multiple silicide types," U.S. Patent Application. Aug. 2006.
• C. Ko, W. Lee, Y. Yeo, C. Lin, and C. Hu, "Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit," U.S. Patent Application. July 2006.
• M. Chi, Y. Yeo, and C. Hu, "Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials," U.S. Patent 7,081,395. July 2006.
• Y. Yeo and C. Hu, "Resistor with reduced leakage," U.S. Patent 7,071,052. July 2006.
• Y. Yeo, P. Wang, H. Chen, F. Yang, and C. Hu, "Doping of semiconductor fin devices," U.S. Patent 7,074,656. July 2006.
• C. Su, P. Tsao, H. Lee, C. Huang, S. Y. Hou, S. P. Jeng, H. Tsai, and C. Hu, "Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling," U.S. Patent Application. July 2006.
• F. Yang, Y. Yeo, H. Tseng, and C. Hu, "Self-aligned contact for silicon-on-insulator devices," U.S. Patent Application. June 2006.
• Y. Yeo and C. Hu, "Resistor with reduced leakage," U.S. Patent Application. June 2006.
• H. C. H. Wang, C. Hu, and C. Lin, "Method for forming devices with multiple spacer widths," U.S. Patent 7,057,237. June 2006.
• Y. Yeo, P. Wang, H. Chen, F. Yang, and C. Hu, "Doping of semiconductor fin devices," U.S. Patent Application. June 2006.
• Y. Yeo, F. Yang, and C. Hu, "Contacts to semiconductor fin devices," U.S. Patent Application. June 2006.
• Y. Yeo, C. Ko, W. Lee, and C. Hu, "Strained channel transistor and methods of manufacture," U.S. Patent 7,052,964. May 2006.
• W. Lee, C. Ge, and C. Hu, "Semiconductor structure having a strained region and a method of fabricating same," U.S. Patent 7,045,836. May 2006.
• C. Lin, W. Lee, C. Hu, S. Chen, C. Wang, F. Yang, and Y. Yeng, "Semiconductor device with high-k gate dielectric," U.S. Patent 7,045,847. May 2006.
• Y. Yeo and C. Hu, "Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric," U.S. Patent 7,037,772. May 2006.
• C. Ge, C. Wang, C. Huang, W. Lee, and C. Hu, "Strained channel on insulator device," U.S. Patent 7,029,994. April 2006.
• C. Ko, Y. Yeo, W. Lee, and C. Hu, "Strained channel complementary field-effect transistors and methods of manufacture," U.S. Patent Application. April 2006.
• W. Lee, C. Ke, and C. Hu, "Semiconductor structure having a strained region and a method of fabricating same," U.S. Patent Application. April 2006.
• C. Huang, C. Wang, C. Ge, and C. Hu, "CMOS device," U.S. Patent 7,022,561. April 2006.
• C. Lin, W. Lee, C. Hu, S. Chen, C. Wang, F. Yang, and Y. Yeo, "Methods of forming semiconductor devices with high-k gate dielectric," U.S. Patent Application. March 2006.
• C. Huang, C. Wang, C. Ge, and C. Hu, "Novel CMOS device," U.S. Patent Application. Feb. 2006.
• Y. Yeo and C. Hu, "Capacitor that includes high permittivity capacitor dielectric," U.S. Patent Application. Jan. 2006.
• Y. Yeo and C. Hu, "SOI chip with recess-resistant buried insulator and method of manufacturing the same," U.S. Patent Application. Dec. 2005.
• Y. Yeo, H. Chen, H. Tsao, F. Yang, and C. Hu, "SOI chip with mesa isolation and recess resistant regions," U.S. Patent 6,979,867. Dec. 2005.
• Y. Yeo, C. Lin, F. Yang, M. Liang, and C. Hu, "Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement," U.S. Patent 6,955,952. Oct. 2005.
• C. Yu, H. Tseng, S. Jang, and C. Hu, "Interconnect with composite barrier layers and method for fabricating the same," U.S. Patent 6,958,291. Oct. 2005.
• Y. Yeo, C. Lin, F. Yang, and C. Hu, "Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer," U.S. Patent 6,953,972. Oct. 2005.
• C. Hu and Y. Yeo, "Suppression of MOSFET gate leakage current," U.S. Patent 6,949,769. Sep. 2005.
• Y. Yeo and C. Hu, "SOI chip with recess-resistant buried insulator and method of manufacturing the same," U.S. Patent 6,949,451. Sep. 2005.
• C. Yu, H. Tseng, S. Jang, and C. Hu, "Interconnect with composite barrier layers and method for fabricating the same," U.S. Patent Application. Sep. 2005.
• C. Ke, W. Lee, Y. Yeo, C. Ko, and C. Hu, "High performance semiconductor devices fabricated with strain-induced processes and methods for making same," U.S. Patent 6,949,443. Sep. 2005.
• Y. Yeo, C. Lin, F. Yang, and C. Hu, "Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer," U.S. Patent Application. Sep. 2005.
• Y. Yeo and C. Hu, "Capacitor with enhanced performance and method of manufacture," U.S. Patent 6,940,705. Sep. 2005.
• Y. Yeo, C. Lin, W. Lee, and C. Hu, "Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof," U.S. Patent Application. Aug. 2005.
• C. Huang, C. Wang, C. Ge, W. Lee, and C. Hu, "Strained silicon layer semiconductor product employing strained insulator layer," U.S. Patent 6,924,181. Aug. 2005.
• Y. Yeo, C. Lin, F. Yang, M. Liang, and C. Hu, "Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement," U.S. Patent Application. Aug. 2005.
• C. Ke, W. Lee, and C. Hu, "Semiconductor structure having selective silicide-induced stress and a method of producing same," U.S. Patent Application. Aug. 2005.
• Y. Yeo and C. Hu, "Capacitor that includes high permittivity capacitor dielectric," U.S. Patent 6,936,881. Aug. 2005.
• Y. Yeo, C. Lin, W. Lee, and C. Hu, "Strained-channel transistor structure with lattice-mismatched zone," U.S. Patent 6,921,913. July 2005.
• C. Wang, C. Tsai, and C. Hu, "Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof," U.S. Patent Application. July 2005.
• C. Ke, W. Lee, Y. Yeo, C. Ko, and C. Hu, "High performance semiconductor devices fabricated with strain-induced processes and methods for making same," U.S. Patent Application. July 2005.
• C. Ge, W. Lee, and C. Hu, "Strained silicon structure," U.S. Patent 6,902,965. June 2005.
• Y. Yeo, F. Yang, and C. Hu, "Semiconductor chip with gate dielectrics for high-performance and low-leakage applications," U.S. Patent 6,906,398. June 2005.
• Y. Yeo and C. Hu, "Capacitor that includes high permittivity capacitor dielectric," U.S. Patent Application. June 2005.
• C. Ge, C. Wang, C. Huang, W. Lee, and C. Hu, "Strained channel on insulator device," U.S. Patent 6,900,502. May 2005.
• Y. Yeo and C. Hu, "Capacitor with enhanced performance and method of manufacture," U.S. Patent Application. May 2005.
• Y. Yeo, C. Ko, W. Lee, and C. Hu, "Strained-channel transistor and methods of manufacture," U.S. Patent 6,882,025. April 2005.
• C. Ke, W. Lee, and C. Hu, "Strained silicon structure," U.S. Patent Application. April 2005.
• H. Chen, Y. Yeo, D. Lee, F. Yang, and C. Hu, "Semiconductor nano-wire devices and methods of fabrication," U.S. Patent Application. April 2005.
• C. Lin, Y. Yeo, C. Huang, C. Wang, T. Chang, C. Hu, F. Yang, S. Chen, M. Liang, and L. Yao, "Relaxed silicon germanium substrate with low defect density," U.S. Patent 6,878,610. April 2005.
• C. Wang, Y. Wang, and C. Hu, "Partial replacement silicide gate," U.S. Patent Application. April 2005.
• Y. Yeo, H. Chen, C. Huang, W. Lee, F. Yang, and C. Hu, "Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors," U.S. Patent 6,867,433. March 2005.
• H. Chen, Y. Yeo, F. Yang, and C. Hu, "Semiconductor device with raised segment," U.S. Patent 6,872,606. March 2005.
• Y. Yeo, H. Chen, H. Tsao, F. Yang, and C. Hu, "SOI chip with mesa isolation and recess resistant regions," U.S. Patent 6,864,149. March 2005.
• C. C. Lin, Y. Yeo, C. Huang, C. Wang, T. Chang, C. Hu, F. Yang, S. Chen, M. Liang, and L. Yao, "Relaxed silicon germanium substrate with low defect density," U.S. Patent Application. March 2005.
• Y. Yeo, C. Hu, and F. Yang, "CMOS SRAM cell configured using multiple-gate transistors," U.S. Patent 6,864,519. March 2005.
• C. Hu and G. Zhang, "Tamper-proof content-playback system offering excellent copyright protection," U.S. Patent Application. Feb. 2005.
• Y. Yeo, F. Yang, and C. Hu, "Strained-channel multiple-gate transistor," U.S. Patent 6,855,990. Feb. 2005.
• H. Chen, Y. Yeo, F. Yang, and C. Hu, "Semiconductor nano-rod devices," U.S. Patent 6,855,606. Feb. 2005.
• H. Chen, Y. Yeo, F. Yang, and C. Hu, "Semiconductor device with raised segment," U.S. Patent Application. Feb. 2005.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," U.S. Patent 6,855,994. Feb. 2005.
• H. Chen, Y. Yeo, F. Yang, and C. Hu, "Semiconductor nano-rod devices," U.S. Patent Application. Jan. 2005.
• H. Tseng, J. Guo, C. Hu, and D. Lin, "Non-floating body device with enhanced performance," U.S. Patent 6,847,098. Jan. 2005.
• Y. Yeo, F. Yang, and C. Hu, "Multiple-gate transistors with improved gate control," U.S. Patent 6,844,238. Jan. 2005.
• H. Tseng, J. Guo, C. Hu, and D. Lin, "Method of fabricating a non-floating body device with enhanced performance," U.S. Patent Application. Jan. 2005.
• C. Hu and Y. Yeo, "Suppression of MOSFET gate leakage current," U.S. Patent 6,830,953. Dec. 2004.
• Y. Yeo, H. Chen, C. Huang, W. Lee, F. Yang, and C. Hu, "Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors," U.S. Patent Application. Nov. 2004.
• C. Huang, Y. Yeo, K. Yang, C. Lin, and C. Hu, "Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance," U.S. Patent 6,812,116. Nov. 2004.
• C. Wan, T. Wang, and C. Hu, "High performance CMOS devices and methods for making same," U.S. Patent Application. Nov. 2004.
• H. Chen, P. Wu, C. Wang, F. Yang, and C. Hu, "CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof," U.S. Patent Application. Nov. 2004.
• C. Lin, W. Lee, Y. Yeo, and C. Hu, "Transistor with a strained region and method of manufacture," U.S. Patent Application. Oct. 2004.
• K. Yang, Y. Chen, H. Chen, F. Yang, and C. Hu, "Method for fabricating a body contact in a FinFET structure and a device including the same," U.S. Patent Application. Oct. 2004.
• B. Yu, C. Hu, Y. King, J. T. Pohlman, and R. Trivedi, "Low-voltage punch-through transient suppressor employing a dual-base structure," U.S. Patent RE38,608. Oct. 2004.
• I. Polishchuk, P. Ranade, T. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," U.S. Patent 6,794,234. Sep. 2004.
• C. Lin, W. Lee, Y. Yeo, and C. Hu, "Device having multiple silicide types and a method for its fabrication," U.S. Patent Application. Sep. 2004.
• H. Chen, Y. Chan, K. Yang, F. Yang, and C. Hu, "Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement," U.S. Patent 6,784,071. Aug. 2004.
• F. Yang, Y. Yeo, H. Chen, T. Tsao, and C. Hu, "Semiconductor-on-insulator chip with <100> oriented transistors," U.S. Patent Application. July 2004.
• C. Huang, Y. Yeo, K. Yang, C. Lin, and C. Hu, "Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance," U.S. Patent Application. July 2004.
• C. Huang, F. Yang, M. Ken, C. Hu, C. Ge, W. Lee, and C. Ko, "Complementary field-effect transistors and methods of manufacture," U.S. Patent Application. July 2004.
• H. Chen, Y. Chan, K. Yang, F. Yang, and C. Hu, "Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement," U.S. Patent Application. July 2004.
• C. Wang, S. Chen, Y. Wang, H. Chiu, L. Yao, and C. Hu, "Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same," U.S. Patent Application. June 2004.
• W. Lee, C. Ge, and C. Hu, "Silicide/semiconductor structure and method of fabrication," U.S. Patent Application. June 2004.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," U.S. Patent 6,753,229. June 2004.
• C. Huang, Y. Yeo, C. Wang, C. Lin, and C. Hu, "Improved cobalt silicidation process for substrates with a silicon germanium layer," U.S. Patent Application. June 2004.
• H. Chen, Y. Yeo, F. Yang, and C. Hu, "Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices," U.S. Patent 6,720,619. April 2004.
• Y. Yeo and C. Hu, "Lithography apparatus for manufacture of integrated circuits," U.S. Patent Application. April 2004.
• Y. Yeo, B. Lin, and C. Hu, "Immersion fluid for immersion lithography, and method of performing immersion lithography," U.S. Patent Application. March 2004.
• Y. Yeo, C. Lin, F. Yang, and C. Hu, "Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer," U.S. Patent 6,703,271. March 2004.
• K. Yang, Y. Chan, Y. Chu, H. Chen, F. Yang, and C. Hu, "High performance PD SOI tunneling-biased MOSFET," U.S. Patent 6,674,130. Jan. 2004.
• C. Wang and C. Hu, "Devices with high-k gate dielectric," U.S. Patent Application. Jan. 2004.
• C. Lin, W. Lee, Y. Yeo, and C. Hu, "Structure and method of forming integrated circuits utilizing strained channel transistors," U.S. Patent Application. Dec. 2003.
• Y. Yeo, F. Yang, and C. Hu, "Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors," U.S. Patent Application. Nov. 2003.
• Y. Yeo, C. Wang, and C. Hu, "Dummy pattern for silicide gate electrode," U.S. Patent Application. Oct. 2003.
• H. Tseng, J. Guo, C. Hu, and D. Lin, "Method of fabricating a non-floating body device with enhanced performance," U.S. Patent 6,627,515. Sep. 2003.
• C. Lin, W. Lee, Y. Yeo, and C. Hu, "Ultra-thin body transistor with recessed silicide contacts," U.S. Patent Application. Aug. 2003.
• C. Huang, C. Ge, W. Lee, C. Hu, C. H. Diaz, and F. Yang, "Strained silicon MOS devices," U.S. Patent Application. Aug. 2003.
• Y. Yeo, F. Yang, and C. Hu, "Semiconductor diode with reduced leakage," U.S. Patent Application. Aug. 2003.
• C. Hu, D. Tang, and H. Tseng, "Semiconductor device with low-k dielectric in close proximity thereto and its method of fabrication," U.S. Patent Application. Aug. 2003.
• G. Zhang, C. Hu, and S. S. Chiang, "Antifuse structure suitable for VLSI application," U.S. Patent 6,603,187. Aug. 2003.
• Y. Yeo and C. Hu, "Capacitor with improved capacitance density and method of manufacture," U.S. Patent Application. July 2003.
• Y. Yeo, F. Yang, and C. Hu, "Accumulation mode multiple gate transistor," U.S. Patent Application. May 2003.
• H. Tseng, D. Lin, K. Yang, and C. Hu, "Method of fabricating a salicided device using a dummy dielectric layer between the source/drain and the gate electrode," U.S. Patent Application. March 2003.
• K. Yang, Y. Chan, Y. Chu, H. Chen, F. Yang, and C. Hu, "High performance PD SOI tunneling-biased MOSFET," U.S. Patent 6,518,105. Feb. 2003.
• C. Huang, C. Wang, C. Ge, and C. Hu, "Novel CMOS device," U.S. Patent Application. Dec. 2002.
• Y. Yeo, F. Yang, and C. Hu, "Method of forming a transistor with a strained channel," U.S. Patent 6,492,216. Dec. 2002.
• Y. Yeo, F. Yang, and C. Hu, "CMOS inverters configured using multiple-gate transistors," U.S. Patent Application. Dec. 2002.
• Y. King, T. King, and C. Hu, "Multiple-thickness gate oxide formed by oxygen implantation," Aug. 2002.
• C. Hu, T. King, V. Subramanian, L. Chang, X. Huang, Y. Choi, J. T. Kedzierski, N. Lindert, J. Bokor, and W. Lee, "FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture," U.S. Patent 6,413,802. July 2002.
• N. W. Cheung, X. Lu, and C. Hu, "Method of separating films from bulk substrates by plasma immersion ion implantation," U.S. Patent 6,344,404. Feb. 2002.
• Y. Yeo, F. Yang, and C. Hu, "MOSFET device with a strained channel," U.S. Patent Application. Feb. 2002.
• C. Hu, M. J. Chan, H. Wann, and P. K. Ko, "Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility," U.S. Patent 6,300,649. Oct. 2001.
• N. W. Cheung, X. Lu, and C. Hu, "Method of separating films from bulk substrates by plasma immersion ion implantation," U.S. Patent Application. May 2001.
• C. Hu, M. J. Chan, H. Wann, and P. K. Ko, "Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility," U.S. Patent 6,121,077. Sep. 2000.
• G. Zhang, C. Hu, and S. S. Chiang, "Antifuse structure suitable for VLSI application," U.S. Patent 6,111,302. Aug. 2000.
• N. W. Cheung, X. Lu, and C. Hu, "Method of separating films from bulk substrates by plasma immersion ion implantation," U.S. Patent 6,027,988. Feb. 2000.
• B. Yu, C. Hu, Y. King, J. T. Pohlman, and R. Trivedi, "Low-voltage punch-through transient suppressor employing a dual-base structure," U.S. Patent 6,015,999. Jan. 2000.
• N. D. Bui, C. Hu, D. Park, and S. Zheng, "Detection of process-induced damage on transistors in real time," U.S. Patent 6,005,409. Dec. 1999.
• C. Hu, M. J. Chan, H. Wann, and P. K. Ko, "Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility," U.S. Patent 5,982,003. Nov. 1999.
• B. Yu, C. Hu, Y. King, J. T. Pohlman, and R. Trivedi, "Low-voltage punch-through transient suppressor employing a dual-base structure," U.S. Patent 5,880,511. March 1999.
• J. C. Chen, Z. Liu, C. Hu, and P. K. Ko, "Realistic worst-case circuit simulation system and method," U.S. Patent 5,790,436. Aug. 1998.
• C. Hu and H. Wann, "Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation," U.S. Patent 5,780,899. July 1998.
• C. Hu and R. Moazzami, "Ferroelectric nonvolatile dynamic random access memory device," U.S. Patent 5,768,182. June 1998.
• A. R. Forouhi, E. Z. Hamdy, C. Hu, and J. L. McCollum, "Electrically programmable antifuse," U.S. Patent 5,670,818. Sep. 1997.
• Y. Wei, Y. T. Loh, C. S. Wang, and C. Hu, "ESD and hot carrier resistant integrated circuit structure," U.S. Patent 5,631,485. May 1997.
• C. Hu and H. Wann, "Method of fabricating a self-aligned high speed MOSFET device," U.S. Patent 5,599,728. Feb. 1997.
• C. Hu, P. K. Ko, F. Assaderaghi, and S. Parke, "Dynamic threshold voltage MOSFET having gate to body connection for ultra-low voltage operation," U.S. Patent 5,559,368. Sep. 1996.
• C. Hu and F. Hsu, "Pseudo-nonvolatile memory incorporating data refresh operation," U.S. Patent 5,511,020. April 1996.
• Y. Wei, Y. T. Loh, C. S. Wang, and C. Hu, "Method of forming an ESD and hot carrier resistant integrated circuit structure," U.S. Patent 5,496,751. March 1996.
• C. Hu, M. J. Chan, H. Wann, and P. K. Ko, "Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility," U.S. Patent 5,489,792. Feb. 1996.
• G. Zhang, C. Hu, and S. S. Chiang, "Antifuse structure suitable for VLSI application," U.S. Patent 5,485,031. Jan. 1996.
• C. Hu and H. Wann, "Capacitorless DRAM device on silicon-on-insulator substrate," U.S. Patent 5,448,513. Sep. 1995.
• A. R. Forouhi, E. Z. Hamdy, C. Hu, and J. L. McCollum, "Electrically programmable antifuse having a metal to metal structure," U.S. Patent 5,387,812. Feb. 1995.
• A. R. Forouhi, E. Z. Hamdy, C. Hu, and J. L. McCollum, "Electrically programmable antifuse and fabrication processes," U.S. Patent 5,272,101. Dec. 1993.
• A. A. Eltoukhy, G. W. Bakker, and C. Hu, "Low voltage programming antifuse and transistor breakdown method for making same," U.S. Patent 5,163,180. Nov. 1992.
• C. Hu and S. P. Sapp, "High voltage power IC process," U.S. Patent 4,908,328. March 1990.
• A. T. Wu, P. K. Ko, T. Chan, and C. Hu, "Electrically programmable memory device employing source side injection," U.S. Patent 4,794,565. Dec. 1988.
• S. T. Wang, C. Hu, and Y. Shum, "Nonvolatile memory cell," U.S. Patent 4,538,246. Aug. 1985.
• C. Hu, "Electrically erasable programmable read only memory," U.S. Patent 4,366,555. Dec. 1982.