S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra, Q. Huang, K. Kovacs, B. Nikolic, R. H. Katz, J. Bachrach, and K. Asanović, "FireSim: FPGA-accelerated Cycle-exact Scale-out System Simulation in the Public Cloud," in Proceedings of the 45th Annual International Symposium on Computer Architecture, ISCA '18, Piscataway, NJ, USA: IEEE Press, 2018, pp. 29--42.
A. Buchan, J. Bachrach, and R. S. Fearing, "Towards a minimal architecture for a printable, modular, and robust sensing skin," in Intelligent Robots and Systems (IROS), 2012 IEEE/RSJ International Conference on, 2012, pp. 33-38.
Technical Reports
K. Asanović, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar, B. Keller, D. Kim, J. Koenig, Y. Lee, E. Love, M. Maas, A. Magyar, H. Mao, M. Moreto, A. Ou, D. A. Patterson, B. Richards, C. Schmidt, S. Twigg, H. Vo, and A. Waterman, "The Rocket Chip Generator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, April 2016.
P. S. Li, A. M. Izraelevitz, and J. Bachrach, "Specification for the FIRRTL Language," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-9, Feb. 2016.
A. Izraelevitz, "Unlocking Design Reuse with Hardware Compiler Frameworks," J. Bachrach, K. Asanović, S. Schleicher, and J. Ragan-Kelley, Eds., EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2019-168, Dec. 2019.