Superb-CSIS 2009 Participants

	Lesia Bilitchenko California State Polytechnic University, Pomona Computer Science Project Title: Creating A Structural, Human readable language for Synthetic Biology
I will be creating a programming language called BOL. BOL will be a human readable structural language designed to represent biological systems to help create genetic programs. It will enable textual description of complex visual systems where visual designs can be converted to text and vice versa. Ultimately, we plan to integrate CLOTHO's visualization capabilities, which other team member are currently working on, with the language. CLOTHO is a software tool that helps synthetic biologists organize, sort, edit and design parts from a fast growing collection of DNA.
Post Doc: Doug Densmore

	Elicek Delgado-Cepero University of South Florida Electrical Engineering Faculty Mentor: Elad Alon Project Title: Design, modeling, and optimization of spirals multilayer inductors in CMOS ICs
Passive elements in CMOS ICs play an important role in high-frequency applications. However, inductors are among the most difficult ones to predict and design. Therefore, it is necessary to find a feasible and flexible design method for spiral inductors. In this project, is becomes critical to understand the necessary trade-off concerning the geometric layout, series resonant frequency (SRF), quality factor (Q), and area of square and hexagonal spirals inductors. As a first part, geometrical programming method would be used to develop an empirical model using polynomials taking into account the magnetic and electric effects suffered by the single-layer spiral inductor at high frequency. Without having to choose a good design starting point, the method would allow the optimization of the inductor at the frequency of interest. Further, the design method would be enhanced by incrementing the number of layers of the inductor. A multilayer inductor would be designed, modeled and simulated as well. A multilayer inductor will provide benefits such as higher inductance values using the same on-chip space or inductor area, and to increase the effective thickness of the inductor resulting in a decrease in the system losses.
Graduate Mentor: Lingkai Kong

	Collin Engstrom Southwest Minnesota State University Computer Science Faculty Mentor: Koushik Sen Project Title: Automatically Correcting Floating Point Errors in Code
In the past few years, large scale scientific computation has grown in usage. With this large volume of calculations in programs comes the potential for lack of precision. This may lead to inaccurate results, overflows, or other negative consequences. To mitigate this problem, one might elect to promote an offending variable in a given program, allowing it more resources to carry out the intended calculations. The dilemma posed by this is that promoting all variables in larger programs may be prohibitive in terms of the drop in performance. If one simply promotes all variables from float to double, for instance, programs that span thousands of lines of code will take longer to compile or execute. The objective, then, is to promote variables only where necessary and leave the others unchanged. By promoting only the variables responsible for an imprecision, it is possible to correct said imprecision without taking away from the program's performance. To determine where promotions are necessary, we use an adaptation of the delta debugging algorithm.
Graduate Mentor: Jacob Burnim

	Victor Garcia University of California, Los Angeles Electrical Engineering Faculty Mentor: Chenming Hu Project Title: Leakage Current in Multi-gate MOSFET/FinFETs
Transistors continue decreasing in size in order to enhance performance and also reduce cost per operation. But we are currently reaching limits, where the current planar MOSFET technology can no longer be scaled due to process technology constraints. FinFETs/ Multi-gate MOSFETs are seen as a viable solution beyond the 22nm technology node as a replacement. Newer devices present us with newer phenomenons that have to be explored in order to commercialize this technology for circuit design applications. This project seeks to further understand the second order effects of FinFETs such as substrate current due to impact ionization and gate induced drain/ source leakage current, etc. TCAD based simulations of the devices with realistic doping profiles will be used for this study. This together with data from real devices will be used to create a model to predict these leakages for various geometries and bias points.
Graduate Mentor: Sriramkumar Venugopalan

	Revarr Johnson University of Alabama Electrical Engineering Faculty Mentor: Krste Asanovic Project Title: A Case for FPGA Architecture Model Execution (FAME)
Given the multicore microprocessor revolution, one can argue that the architecture research community needs a dramatic increase in simulation capacity. It is considered that FPGA Architecture Model Execution (FAME) simulators can increase the number of useful architecture research experiments per day by more than a factor of 1000 over Software Architecture Model Execution (SAME) simulators. We demonstrate this performance claim with a case study of the impact of automatic clock frequency scaling on power and performance on a collection of parallel programs simulating on 64-core target architecture on a FAME simulator. The first of these programs to be tested is the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark program, a multithreaded benchmark program designed for multiprocessors.
Graduate Mentor: Andrew Waterman

	David Mills University of South Carolina Computer Information Systems Faculty Mentor: Armando Fox Project Title: Workload Generation for Scalable Social Computing Applications
A major challenge for developers of large scale social computing applications is generating a realistic workload to test the ability of their systems to scale. Social Computing sites such as Facebook, Twitter, and Flickr experience a high influx of new users which induces a load on server processing. As server load increases, many unexpected performance bottlenecks occur. The Web 2.0 development model demands the ability to rapidly deploy new features and automatically scale with the number of users. To test the scalability of these applications before production, an innovative workload generator is needed. This research proposes the development of a flexible, developer-friendly workload generator, that enhances the capabilities of the developer, and generate user representative workloads. While past workload generator attempts have focused primarily on testing server capabilities, this study adds emphasis to testing the scalability of the Web Application. It intakes developer specific statistics in the form of a mix matrix for site traversals, and grants developers control of the number of users as well as “think time”. The workload generator will be deployed to the Amazon Elastic Compute Cloud(EC2) which will allow creation of loads that simulate multiple users accessing the server simultaneously. It will act as a testing mechanism for various Web 2.0 Applications.
Graduate Mentor: Beth Trushkowsky

	Tremaine Rawls Norfolk State University Computer Science Faculty Mentor: Claire Tomlin Project Title: State Space Division for Non-Parametric Estimation
State space division for the graph-epsilon partition problem is to partition the nodes of a graph so that the maximum edge weight in the cut is minimized where each state of the system corresponds to a unique point in the state space and the subjective value epsilon ?. The common graph partition problem separates the nodes where the sum of the edge weights in the cut is to be minimized and split into equal sets, and is NP-complete. Although any given solution to such a problem can be verified quickly, there is no known efficient way to locate a solution in the first place; indeed, the most notable characteristic of NP-complete problems is that no fast solution to them is known. That is, the time required to solve the problem using any currently known algorithm increases very quickly as the size of the problem grows. As a result, the time required to solve even moderately large versions of many of these problems easily reaches into the billions or trillions of years, using any amount of computing power available today. This paper is an attempt to remedy the situation by introducing algorithms to partition a state space to properly balance the trade-offs between computational complexity and approximation error in polynomial time. The algorithms will make use of graph theoretic algorithms and approaches and solve the graph-epsilon partition problem.
Graduate Mentor: Anil Awsani

	Samuel Rivera-Gomez University of Puerto Rico-Mayaguez Computer Engineering Faculty Mentor: David Culler Project Title: Load-Disaggregation for Increased Coverage in a Building Energy Auditing Network
Buildings in the United States currently consume approximately 72% of energy in the United States [1], and 30% of it is wasted [2]. With the specter of global warming it is of paramount importance that building energy consumption be reduced and optimized. In this work, we study the data gathered from a set of wireless and wired sensors to disaggregate the power usage of energy consumers within a building. In order to obtain more fine-grained view of the energy consumption, we decompose the data spatio-temporally by individual appliance and across appliances such as laptops, desktops, and monitors. We identify the various components and behaviors within and across individual appliances and apply various techniques, such as non-intrusive load monitoring, to infer who is consuming what, where, and how much is consumed. Such inferences allow us to reduce the cost of deployment, while also identifying optimization and reduction opportunities for building energy consumption.
Graduate Mentor: Jorge Ortiz

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Superb-CSIS 2009 Participants