Architectures and VLSI Implementations of High Throughput of Iterative Decoders

This research addresses the algorithms and implementations of iterative decoders for error control in communication applications. The iterative codes are based on various concatenated schemes of convolutional codes [1], and low-density parity check (LDPC) codes [2]. The decoding algorithms are instances of message passing or belief propagation [3] algorithms, which rely on the iterative cooperation between soft-decoding modules known as soft-input-soft-output (SISO) decoders.

Implementation constraints imposed on iterative decoders applying the message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are contrasted against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of their suitability for VLSI implementation in addition to the performance as measured by bit-error rate as a function of SNR.

In this research, the computational hardware and memory requirements of magnetic storage applications [4] provide a platform for evaluation of the iterative decoders. Past accomplishments include modification of known algorithms to accentuate the physical design considerations. A VLSI implementation of a soft-output Viterbi decoder suitable for high throughput Turbo applications has been demonstrated [5]. The ongoing efforts continue to study and demonstrate the traits of particular low-density parity check codes that lend themselves to efficient mapping on hardware architectures.

[1]

C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo Codes,” Proc. IEEE Int. Conf. Communications, Geneva, Switzerland, May 1993.

[2]

R. G. Gallager, “Low Density Parity Check Codes,” IRE Trans. Information Theory, Vol. 8, January 1962.

[3]

S. M. Aji and R. J. McEliece, "The Generalized Distributive Law," IEEE Trans. Information Theory, Vol. 46, No. 2, March 2000.

[4]

E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, "VLSI Architectures for Iterative Decoders in Magnetic Recording Channels," IEEE Trans. Magnetics, Vol. 37, No. 2, March 2001.

[5]

E. Yeo, S. Augsburger, W. R. Davis, and B. Nikolic, "500 Mb/s Soft Output Viterbi Decoder," Proc. IEEE European Solid-State Circuit Conf., Firenze, Italy, September 2002.