| Conflict-driven Learning in a 0-1 ILP Solver | Donald Chai |
| Fishbone: A Block-level Placement and Routing Scheme | Fan Mo |
| PLA-based Regular Structures and Their Synthesis | Fan Mo |
| Reducing Multi-Valued Algebraic Operations to Binary |
Jie-Hong R. Jiang Alan Mishchenko |
| Sequential Equivalence Verification in the Sum State Space | Jie-Hong R. Jiang |
| Performance Estimation and Floorplanning for Globally Asynchronous Design | Philip Chong |
| Wireplanning in Logic Synthesis | Satrajit Chatterjee |
| MVSIS |
Jie-Hong Jiang Yunjian Jiang Yinghua Li Donald Chai Alan Mishchenko Tiziano Villa |
| Optimal Code Generation for Sequential Logic | Yunjian Jiang |