List of Abstracts for Kurt Keutzer

The EECS Research Summary for 2003

Globally Optimal Power Minimization with Multiple Supply Voltages, Multiple Threshold Voltages, and Gate Sizing with Skewed Drive Strengths	David Chinnery Michael Orshansky
Closing the Gap between ASIC and Custom Power	David Chinnery
Low Power Circuit Synthesis for Advanced Manufacturing Technologies	David Nguyen Abhijit Davare Michael Orshansky
Low Power Design Strategies for High Performance ASSPs and ASICs	Farhana Sheikh
Systematically Exploring the Design Space of Network Processors	Matthias Gries Chidamber Kulkarni Christian Sauer
A Probabilistic Model for Static Timing Analysis of Combinational Circuits	Michael Orshansky Kaushik Ravindran
Identification of Architectural Bottlenecks in Programming Network Processors	Chidamber Kulkarni Christian Sauer Matthias Gries
Mapping Concurrent Applications onto Architectural Platforms	Andrew Mihal
Tools, Languages, and Compilers for Constraint-based Functional Hardware and Software Design	Matthew Moskewicz
Path Categorization Criteria for Static Timing Analysis	Alessandra Nardi Luca Carloni
A Programming Model for Network Processors	Niraj Shah William Plishker
Refining Switching Window by Time Slots for Crosstalk Noise Calculation	Pinhong Chen
On the Convergence of Switching Windows Computation in the Presence of Crosstalk Noise	Pinhong Chen
Automation and Optimizations for a Programming Model for Network Processors	William Plishker Niraj Shah
Programmable Peripherals	Christian Sauer Chidamber Kulkarni Matthias Gries
Correct by Construction Programmable Platforms	Scott Weber
Memory Architecture	Yujia Jin

(17 abstracts total)