Figure 1: Picture of the AFM setup
1Graduate Student (non-EECS), Cornell University
Transistor scaling below 50 nm gate lengths will likely require the incorporation of new device structures in order to adequately control short-channel effects. A promising candidate is the FinFET, a double-gate MOSFET structure [1,2]. The device consists of self-aligned double gates surrounding a thin silicon slab (the “fin”), which can sufficiently suppress short-channel effects.
Thus far, device fabrication has taken place in a research environment and can consequently make use of non-standard tools such as electron beam lithography. In this work, a manufacturable FinFET process is developed using standard processing tools found in an industrial fabrication facility. Critical process steps have been evaluated using short-loop experiments, and initial device results have been obtained. Working transistors down to 10 nm in gate length have been successfully fabricated. Continued work will focus on achieving appropriate threshold voltages in order to study circuit performance.
One of technological challenges for thin body MOSFETs is threshold voltage (Vt) control. Ideally, the FinFET body should be lightly doped in order to achieve high carrier mobility for high transistor drive current, as well as immunity to dopant-fluctuation-induced variations in Vt. The required range of gate work functions for a fully-depleted CMOS FinFET technology is 4.4 V (NMOS) ~ 5.0 V (PMOS), which precludes poly-Si as a gate material. A metal gate with a tunable technology and dual gate work function was announced [1-4]. However, manufacturability and reliability of a gate dielectric should be considered for implementation of metal gate technology to FinFETs.
In this work, molybdenum (Mo) will be used for PMOS and Mo2N will be used for NMOS gate material after selective nitrogen implantation and annealing. Multiple threshold voltages can be achieved by changing a dosage of nitrogen. As an alternative, separated double gates at narrow silicon fins will be formed by chemical-mechanical polishing. Threshold voltages can be adjusted by different gate biases at both gates.
A thin body (<10 nm) is essential for sub 50 nm MOSFETs. Our work with the planarized solid-phase epitaxy process succeeded in 2000. This year we will use a dummy layer on the SPE film to improve the crystalline quality of the channel. After selectively removing the dummy layer, we can get excellent channel film while keeping its ultra-thin thickness. Better device performance is expected from this new fabrication technique.
Besides the process difficulties associated with the ultra-thin body, the control of the threshold voltage becomes a big issue for ultra-thin body devices, because the body doping is not effective in tuning the threshold voltage. Gate work function is believed to be the only method for the right Vt. Various metal gates and silicide gates are going to be tested for the right work function and CMOS process compatibility. Silicide gate with various types of doping shows a continuous range of work function, which makes the material perfect as a gate. With the primitive result we have, silicide gate covers the work function range required by UTB and FinFET devices. Fabrication is in progress.
An analytical model for fully depleted thin SOI and double gate MOSFET is also in progress. We solve the Poisson equation in the thin body and can calculate the 2D potential profile. We investigate the effect of the high k dielectric and pocket doping. We can use the analytical results as a guide for device designing, incluing the device dimensions and doping profile.
Gate line edge roughness (LER) is the random deviation of gate line edges from an ideal definition. It can be produced in lithography and etching steps. LER does not scale down with line width and only reduces with improved process conditions. Recently, as the industry is pushing their logic development toward sub-50 nm physical gate lengths, gate LER is an increasing concern, for it potentially affects circuit performance and reliability. The LER effects on MOSFET device performance have been studied by us and several other research groups through device simulation. In cooperation with AMD, we also performed an experimental study of the effects of gate line edge roughness on the electrical characteristics of bulk MOSFET devices. The physical gate length of the devices ranged from 0.76 µm to 30 nm. Pronounced difference of the gate line edge roughness was introduced using special lithographical techniques. Poly gate LER was characterized with SEM in an approach we developed. In electrical characterization, we compared device data with different gate line edge roughness. We studied the yield, threshold voltages, and DIBL as well as the current universal curves of both NMOS and PMOS devices. The detailed results will be reported in our publication.
As the gate length of MOSFET devices shrinks down below 20 nm, double-gate device structures are emerging as a strong candidate, even considering the added process complexity. This is because double-gate structures have better control of the short channel effect and near ideal turn-off slope. A much lower leakage level can be maintained even with very small gate length. The FINFET device, which is a vertical double-gate MOSFET, has demonstrated such potential capability experimentally. Using device simulations, we have investigated the effects of process variations on the electrical behaviors of 20 nm symmetric double-gate MOSFET devices designed for low power application. First, we studied the effect of doping profile fluctuation. Double-gate devices with poly silicon gates must have very high channel doping in order to reach the desired threshold voltage. In this case, we find the 3s value of VT variation caused by random impurity placement could be very large. This confirmed the effort of our group to engineer the work function of gate materials and maintain low or intrinsic channel doping in FINFET devices. Second, based on the device design with intrinsic channel and ideal gate work function, we analyzed the change of device electrical parameters caused by the variations on physical parameters such as gate length, body thickness, and gate dielectric thickness. We found that quantum effect has great impact on the performance of devices at this scale. The device electrical behavior is most sensitive to small variations in body thickness while the variations of effective channel length and other physical parameters are less critical. Based on these results, we gave predictive estimation on the tolerance of the device to different process variations in circuit application.
I am also targeting to study the effect of process variation on circuit performance and carrier transport in the channel of FINFET devices. I will devote my research to developing techniques and collecting experimental data in this study.
This project is one part of a large project named Integrated Microwatt Transceivers launched this summer at BSAC at UC Berkeley. The aim of the whole project is to do the research on the architecture, circuit design, and fabrication technologies for integrated transceivers that exploit the analog signal processing capabilities of banks of nanomechanical filters. The requirements for the nanomechanical filter banks are to have an insertion loss of less than a few dB and a Q on the order of 10,000 in the carrier frequency range, which is 1-2 GHz in the near term and 5-10 GHz or higher in the future wireless sensor networks. The purpose of our project is to characterize the nanomechanical resonators by interferometer or atomic force microscope (AFM) combined with optical actuation.The result we got so far is the measurement by AFM of the out-of-plane movement of the film bulk acoustic resonator (FBAR) around its resonant frequency, i.e., 1.96 GHz.
Figure 1: Picture of the AFM setup
1Graduate Student (non-EECS), Cornell University
The fabrication of nanoscale patterns below 10 nm has been a goal of many researchers for potential applications such as sensors, soft X-ray optical device components, electronic circuit elements, or catalysts. Electron beam lithography is the most commonly used technique for nanometer pattern generation. However, the generation of secondary electrons during electron bombardment makes it difficult to achieve sub-10 nm patterning. Electron beam lithography is also a sequential pattern producing technique and is very time-consuming compared to photolithography-based processes that produce the whole pattern at once using a mask. This is also the case for other scanning probe based lithography techniques. In this work two sub-lithographic patterning technologies, spacer lithography and nanosphere lithography, will be studied. Spacer lithography using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer was demonstrated [1,2]. Sacrificial layers (to support the spacers) were initially defined by conventional lithography and plasma etching. Then, another thin CVD layer that would be spacers was deposited and etched back. After removal of sacrificial structures, these spacers were transferred to a substrate with anisotropic plasma etch. Thus, minimum-sized features were defined not by photoresist but by sidewall spacers deposited by CVD. One of the benefits in the spacer lithography is that it doubles the pattern density achievable by lithography. If this spacer lithography is used n times in succession, 2n lines can generated from a single lithographically defined line. With nanoimprint technology, Pt nanowires and Pt nanoparticles can be fabricated by the spacer lithogrpahy for catalysts and nanowires composed of other materials can be used for chemical and biosensors. Nanopshere lithography uses a monolayer of nanobeads, which are coated by a spinning process [3]. Well-ordered nanogaps can be formed by these adjacent nanobeads. Combining the nanosphere lithography with a metal lift-off process, nanosize metal particles can be patterned, which can be used as catalysts for carbon nanotube growth and as an etch stopper to make nanopillars. The packed nanobeads can also be served as an etch stopper to make nanoholes.
Wafer bonding is an enabling technology for materials integration in microelectronics, optoelectronics, and MEM systems [1]. Although most published work focuses on forming a permanent bond between two wafers, a growing aspect of bonding involves the use of temporary or controlled bonding, so called "post-it" style bonding. Surface nano-texturing could be a way to engineer the bond to a prescribed strength. Recently, we described the surface textures produced by low energy Ar ion sputtering under various experimental conditions. An important feature is that nanometer scale ripples can be formed, with a wave vector either parallel or perpendicular to the projected direction of ion beam. The surface topography is characterized by atomic force microscopy (AFM), and topography parameters are extracted as functions of incidence angle, ion energy, and dose .In 2003, we will focus on the correlation of the delamination energy (measured by the crack opening method) with the topography parameters.
One of the major challenges in realizing fluorescence-based lab-on-a-chip or micro-total analysis systems (m-TAS) by heterogeneous integration of the necessary components such as light sources, microfluidic channels, optical filters, and photodetectors, is the direct integration of the light source into the system. The ability to integrate multi-color narrow-band sources that are spatially distributed so as to operate in the near field would provide functionality on a chip that is currently only feasible with benchtop instruments.
We have developed a novel pixel-to-point transfer process to integrate GaN light-emitting diodes with photodetector chips and thin-film band-edge filters. This integration process was enabled by the double transfer technique [1] (Figure 1) which we previously developed for integration of GaN light-emitting diode (LED) arrays with silicon substrates. The pixel-to-point transfer process solved problems of pixel pick-up from the source wafer and pixel registration to the target system. The transfer was accomplished by (1) temporarily bonding the LED pixel to a specially designed pick-up rod with sapphire substrates facing upward using Super Glue®, (2) removing the sapphire substrates using laser lift-off, and (3) permanently bonding the LED pixel to the designated area in the pre-fabricated silicon photodiodes using Pd-In transient-liquid-phase bonding.
Using the pixel-to-point transfer process, we are now fabricating a prototype light-source/detector chip based on fluorescence devices to evaluate the performance of the integrated biochips. A GaN LED with peak emission at 463 nm will be used to excite 515 nm fluorescence from FluoSpheres® carboxylate-modified yellow-green fluorescent microspheres (40 nm in diameter).
Figure 1: General scheme of double transfer process
Semiconductor memories such as DRAM play an increasingly important part in determining the performance of microelectronic products. Their role has raised the demand for reliable, high density memories with fast data access and low power consumption. However, significant challenges must be overcome in scaling DRAM. Reducing the transistor's off-state leakage, for example, can require high substrate doping to sustain a large threshold voltage. Unfortunately, this approach enhances trap-assisted tunneling and leads to tail bits with small retention times. Another problem is the integration of a small storage capacitor in a technology which should provide an adequate sensing signal margin, long retention time, and soft error protection. As a result, it is unclear if DRAM can scale below feature sizes of 100 nm without changes in the standard 1 transistor/1 capacitor (1T/1C) cell design.
In this study, we investigate three new approaches at scaling DRAM. First, double-gate DRAM (DG-DRAM) is a new memory technology which embodies a thin body, double-gate structure. Scalability is intrinsic to its unique, compact design. We have compared DG-DRAM against other capacitorless DRAM technologies, considered variations in its cell design, performed experimental and simulation measurements, and explored soft error problems. In addition, two other capacitorless memory concepts are investigated. These include an improved version of a direct tunneling floating gate device, featuring a large threshold voltage window and superior data retention. A new direct tunneling, trap-based memory technology is also developed using conventional CMOS materials. These ideas represent novel and manufacturable approaches at bridging the gap between current CMOS memories and future technologies.
Controllability of off-state leakage current, with retention of large on-state drive current, is the primary challenge for scaling complementary metal oxide semiconductor (CMOS) transistor gate lengths into the nanoscale regime. Fully depleted ultra-thin-body (UTB) SOI metal oxide semiconductor field effect transistor (MOSFET) structures provide excellent suppression of short channel effects and performance improvement, and hence are promising for sub-70 nm CMOS technology [1]. In order to avoid mobility degradation and threshold-voltage (VT) variation due to channel dopant fluctuations, it is desirable to use an undoped or very lightly doped (<1017 cm-3) silicon body. In this case, VT adjustment must be achieved by gate work function engineering, in the range from 4.4-5.0 V for a fully depleted SOI CMOS technology [2]. Ideally, the technique for adjusting the gate work function should not utilize common dopants in Si, in order to avoid problems due to dopant penetration through ultra-thin gate dielectrics during the source/drain (S/D) annealing step(s). These requirements essentially rule out polycrystalline silicon (poly-Si) as a candidate gate material for nanoscale UTB SOI CMOSFETs. For simplicity of process integration, it is preferable to deposit a single gate material and subsequently adjust its work function selectively (e.g., in the n-channel vs. p-channel regions) as required. Molybdenum (Mo) is applied as the gate material to achieve the proper VT (-0.2 V) in p-channel UTB SOI MOSFETs for the first time, and VT adjustment via nitrogen implantation is demonstrated. Continued work will focus on investigating the statistical variation of the threshold voltage due to the nitrogen implantation and achieving appropriate threshold voltages with high-K dielectric (HfO2).
The main barrier to full exploitation of SOI/CMOS performance and power is that the design and fabrication of a dedicated chip is a risky process because present tools are neither accurate enough nor efficient enough for fast turnaround and high probability of first-pass success. In this project we address the model accuracy issue. A critical element of all integrated system designs is the SPICE model. SPICE modeling is the standard approach for precise design of critical-path subcircuits in all large systems, as well as the basis for computing the look-up tables used for higher-level timing simulation. Recent versions of the BSIM3 model, based on the physics of short channel MOSFETs, very accurately represent the behavior of the current generation of bulk silicon devices at frequencies up to around 1 GHz. However, current models are inadequate for frequencies much above that, because the intrinsic input resistance and substrate resistance are ignored. Furthermore, the best widely available SOI model, BSIMSOI, does not represent floating body behavior accurately enough to simulate correct output characteristics of fully depleted (FD)SOI devices even at DC, and little is known of the SOI body charging effect at >1 GHz. We will develop an improved FDSOI model based on the existing BSIMSOI model. FDSOI transistors will be fabricated at MIT's Lincoln Laboratory with gate lengths of 180 nm and up, and they will be characterized by both DC and S-parameter measurements at frequencies up to 50 GHz. A new model which includes intrinsic input resistance and SOI floating body effects will be developed at UC Berkeley. The effort will focus initially on DC behavior and then move to representation of RF effects at a frequency of at least 10 GHz.
1Staff, MIT Lincoln Lab
2Visiting Professor, Hong Kong University of Science and Technology
Scaling and high performance advantages make SOI an important CMOS technology. However, the main barrier to full exploitation of SOI performance and power is that the design of an SOI chip is a relatively risky process because the relative lack of design experience makes it difficult to achieve fast turnaround and high probability of first-pass success. To surmount this barrier, a robust and physically accurate SPICE (compact) model is needed. SPICE modeling is the standard approach for precise design of critical-path sub-circuits in all large systems, as well as the basis for computing the look-up tables used in higher-level timing simulators. Cell libraries and IP blocks are in turn designed using the speedier simulations. A compact SOI MOSFET model is crucial to SOI circuit design. The goal of this work, therefore, is to establish a standard SOI model for the semiconductor industry.
1Visiting Professor, Hong Kong University of Science and Technology
As the microelectronics industry is fast approaching the limit of bulk CMOS scaling, there are extensive research activities on double-gate MOSFETs which can potentially further extend CMOS scaling to 10 nm gate dimensions. The topology of the double-gate device is fundamentally different from that of a bulk or SOI device in that the second gate can be either tied together with the first gate or biased separately. The implications of the additional feature on circuit performance need to be understood and evaluated at the circuit level with a sound compact model. As a result, there is a strong demand on a compact model that can be implemented into the existing circuit simulation infrastructure.
The goal of this project is to develop a generic non-structural dependent compact model for double-gate CMOS, implemented in the BSIM framework. The model will be physics-based and general enough to cover various structures of double-gate MOSFETs. The model will also account for arbitrary work functions and separately controlled gates. From a circuit application perspective, the compact model will be widely applicable to different biasing schemes, e.g., both gates switching or separately biased (DC or AC). The ultimate objective is to provide a predictive yet versatile tool for circuit designers to evaluate the performance benefits of the general and specific features of a double-gate MOSFET technology, thus giving a guideline to the selection of double-gate structures.
1Visiting Professor, Hong Kong University of Science & Technology
Monolithic integration of MEMS devices with driving and controlling electronics is advantageous for improving performance and potentially lowering cost. Polycrystalline silicon-germanium (poly-Si(l-x)Ge(x), where x is between 0 and 1), which has mechanical and electrical properties similar to poly-Si, is a promising candidate for the structural-layer material of post-CMOS integration of MEMS because poly-SiGe can be deposited (and annealed, if necessary) at much lower temperatures than poly-Si. To be successfully integrated with state-of-the-art electronics fabricated by IC foundries, any post-CMOS MEMS process with temperature higher than 450°C must be avoided.
While low-resistivity poly-SiGe can be easily obtained utilizing in situ p-type (i.e., boron) doping during deposition, poly-SiGe films as-deposited at 450°C or lower generally exhibit some level of residual stress and strain gradient. For optical switching/modulation and inertial-sensing applications, residual stress and strain gradient of the structural layers have to be minimized. From previous experimental results [1], it has been found that the stress and strain gradient of as-deposited poly-SiGe are dependent on deposition conditions, including temperature, pressure, and germanium content.
A full-factorial experiment was conducted to investigate the optimal deposition condition to achieve low stress and low strain gradient. Low residual stress (-9 MPa, compressive) and low strain gradient (2.4E-5µm-1) was achieved in as-deposited 2 µm poly-Si0.4Ge0.6 film deposited at 450°C and 600 mT. The residual stress and strain gradient were each generally found to increase significantly with decreasing deposition temperature. A 2 µm poly-Si0.4Ge0.6 film deposited at 425°C exhibited -45 MPa stress and 3E-4µm-1 strain gradient.
To further bring down the effective strain gradient, a bi-layer approach is currently under investigation. By depositing film with compressive stress on top of film with tensile stress, a bending-down moment can be created to cancel out the bending-up moment in general as-deposited films. Stress cancellation between two layers can also further lower the effective residual stress.
HfO2 is one of the most promising candidates to replace SiO2 as the gate dielectric because of its high permittivity, thermodynamic stability, and large energy-bandgap offset to Si. For simplicity of process integration, polycrystalline silicon (poly-Si) is preferred as a gate electrode material. However, the growth of an interfacial layer at the surface of the silicon upon high-temperature annealing (e.g., used for source/drain formation) increases the equivalent oxide thickness (EOT) and gate leakage current [1].
Polycrystalline silicon-germanium (poly-SiGe) has received much attention as an alternative gate-electrode material, because it alleviates gate depletion and boron penetration issues [2]. Recently, it was reported that the use of poly-SiGe results in thinner EOT for HfO2 gate dielectric [3].
We investigate the mechanism responsible for this effect. Using MOS capacitors, the effect of the gate material and gate deposition rate on interfacial layer formation is studied. A conventional LPCVD furnace was used to deposit the gate materials (poly-Si and poly-Si0.8Ge0.2) at 550°C onto PVD HfO2 gate dielectric. The effect of gate deposition rate was studied by comparing the results for poly-Si deposited using SiH4 against those for poly-Si deposited using Si2H6. (The deposition rate for poly-Si using Si2H6 is about 8 times faster than that for poly-Si using SiH4; the deposition rate for Si0.8Ge0.2 is about 7 times faster than that for poly-Si using SiH4).
In a conventional CMOS process, polycrystalline-silicon doped heavily by ion implantation is used as the gate material. Thermal annealing (either in a furnace or rapid thermal annealer) is carried out to activate the dopants. However, due to the non-uniform implanted dopant profile and thermal budget constraints, it is difficult to achieve very high active dopant concentration (>10E20 cm-3) at the gate/dielectric interface. As a result, the lower portion of the gate electrode is depleted when the MOSFET is turned on, effectively increasing the thickness of the gate dielectric and thereby degrading the transistor drive current. The gate-depletion problem becomes significant as the equivalent oxide thickness (EOT) is scaled below 2 nm and the power-supply voltage is reduced to 1 V and below, and hence is a serious problem for sub-90 nm CMOS technologies.
In this project, pulsed (~30 ns) excimer laser (248 nm) annealing (ELA) is being investigated as a means to achieve high active dopant concentration with minimal thermal budget. The gate material is deposited in amorphous form (to provide a low melting temperature) and then implanted with dopants. An excimer laser pulse is then applied to momentarily melt the gate layer. In the melt, the dopants redistribute rapidly, resulting in a box-shaped concentration profile. The rapid cooling and crystallization process yields an active dopant concentration higher than the solid solubility limit. Thus, the gate depletion problem can be greatly alleviated.
Both n-channel and p-channel MOS devices will be fabricated using Si(1-x)Ge(x) (x=0, 0.2, or 0.4) as the gate material. The purpose of using a silicon-germanium alloy is to lower the gate melting temperature. (For example, the melting point of amorphous Si0.8Ge0.2 is estimated to be ~1000°C.) This may be needed in order for the ELA process to be used in conjunction with a high-permittivity gate dielectric material. The effect of ELA on gate sheet resistance, gate depletion, gate leakage, and gate-dielectric reliability will be monitored as a function of laser fluence for the various gate materials.
I propose that ultra-thin silicon nitride films be used to create abrupt junctions between n-type and p-type regions in microelectronic devices. These films should block unwanted boron diffusion. With a thickness of around 1 nm, the nitride layers should also be thin enough to allow charge carriers to tunnel through, thus causing minimal impact on electrical characteristics.
Two experimental stages will be necessary in order to determine whether silicon nitride can be a diffusion barrier to boron while allowing charge carriers to tunnel. First it will be necessary to find the fabrication parameters that will produce an ultra-thin silicon nitride film which blocks boron diffusion. Then it will be essential to optimize the electrical behavior of a device which has a nitride layer between its n- and p-regions.
Selective deposition of SiGe is advantageous for making a raised S/D FinFET with very low parasitic resistance, particularly needed for analog circuit applications. Ideally, the Ge content should be limited to less than 50% to simplify the S/D silicidation process. In this project, we will explore the use of Cl2 gas to enhance the selective deposition of low-Ge-content films on Si (vs. SiO2 or Si3N4) in a conventional LPCVD furnace. The chlorine is expected to promote selective deposition by removing ad-atoms on the insulator surface via SiCl2 or GeCl2 desorption, at temperatures above 700°or 400°, respectively. The gas flow ratios and process temperature will be optimized for high selectivity of deposition.
As the double-gate MOSFET (DG-MOSFET) structure is adopted for CMOS IC manufacturing in the sub-30 nm gate-length regime, the effects of process-induced variations on DG-MOSFET characteristics become very critical. In this research, we compare n-channel symmetric-double-gate (SDG) and asymmetric-double-gate (ADG) devices with nominal gate length of 9 nm in terms of their tolerance to process induced variations. The SDG device is assumed to have a gate material with work function 4.486 eV, while the ADG device is assumed to have n+/p+ poly-Si front-gate/back-gate. MEDICI device simulation is used, with a drift diffusion model for carrier transport and a realistic device structure based on ITRS specifications for the 9 nm technology generation. The results show that both ADG and SDG have acceptable performance within 25% bottom gate misalignment, 10% CD variation, and 5% Tsi variation. Thus, ADG and SDG are both fairly tolerant to process-induced variations. Quantum-confinement effects are more severe in the case of the ADG device and can be dominant for ultra-thin body thickness Tsi, however. Overall, the SDG structure seems to be more advantageous, which implies that metal gate technology will be needed to fully tap the circuit-performance benefits of the DG MOSFET structure.
Polycrystalline Silicon (Poly Si) has been commonly used for micro electromechanical systems (MEMS) applications, yet the main drawback of this material is that it requires a high processing temperature (higher than 800°C) in order to achieve the required mechanical properties. Such a temperature is too high when MEMS devices are fabricated after the electronics circuitry (especially if non refractory metals are used for CMOS back end technology). On the other hand, Poly-SiGe material has physical properties comparable to those of Poly-Si, yet it can be processed at low enough temperature to avoid damage on chips electronics. This makes Poly-SiGe very attractive for the integration of MEMS after standard electronics.
In order to achieve an optimal integration of MEMS devices with CMOS circuitry, the electrical connection between the MEMS and the electronics circuit needs to introduce the minimum possible interconnect parasitics. Therefore, direct deposition of SiGe onto metal is desirable. In addition, the specific contact resistivity between the two materials needs to be low enough, allowing it to be comparable to the state-of-the-art specific interconnect resistivity requirement (less than 1 ohm-cm2).
Using the well-known Kelvin structures, research of SiGe deposition on metal films is continuing with the prospect of determining the contact resistivity of p+ SiGe films deposited onto TiN of different contact area sizes. We are also interested to see how increasing or decreasing SiGe processing temperature (between 400°C and 450°C) affects the contact resistivity. The initial results obtained from the contact resistance measurements are very promising. Depending on the contact hole dimensions as well as the SiGe deposition temperature, it is possible to reduce the specific contact resistivity to less than 1 ohm-cm2. One of the main issues we've encountered is a proper cleaning process of the wafers prior to SiGe deposition. This is critical as it helps to achieve a good interface between SiGe and the metal film beneath, thus reducing the contact resistance. Using Argon Sputtering plasma rather than Helium plasma, we observed that the contact resistivity could also be reduced.
As the dimensions of semiconductor devices are scaled down in order to achieve higher levels of integration, optical lithography will no longer be sufficient for the needs of the semiconductor industry. There are some challenging issues with complicated mask technology and low throughput for some alternative lithography technologies such as X-ray, EUV, electron-beam lithography, etc. Focused ion beam (FIB) patterning of films is a well-established technique (e.g., for mask repair), but throughput has historically been a prohibitive issue in its application to lithographic processes in semiconductor manufacturing. The goal of this project is to develop a focused ion beam system for high-throughput resistless, direct patterning, and doping of films that can be made practical for high-volume production.
The compact FIB system being developed uses a multicusp plasma ion source and a novel electrostatic accelerator column. The multicusp plasma source can generate ion beams of various elements, such as O2+, BF2+, P+ etc., for surface modification and doping applications.
The beam brightness of a multicusp-plasma ion source has been substantially improved by optimizing the source configuration and extractor geometry. Measured beam brightness can be as high as 440 A/cm2Sr, which represents a 30 times improvement over previous work.
A multiple-beam system will be built by stacking multi-aperture electrode-insulator structure so that each beam is accelerated with the same electrode potentials. Parallel processing with multiple beams can greatly enhance the throughput of a FIB system.
We have investigated the process for direct patterning using focused O2+ ion beam. A thin surface oxide film on an Si wafer can be selectively formed using low energy focused O2+ ion beam. It can then serve as a hard mask for patterning of the Si film. We also investigated the formation of doped regions in bulk silicon wafers by scanning focused P+ beam implantation. To demonstrate the suitability of scanning FIB lithography for the manufacture of integrated circuits, the SOI MOSFET device fabrication using the process developed to pattern gate electrode and form source/drain region is in progress.
Double-gate (DG) MOSFETs are a proposed solution to extended CMOS scaling beyond bulk-Si MOSFETs. A variety of DG structures have been proposed [1]. Vertical structures, such as the FinFET have a layout penalty related to the routing of wires to both the gates. A planar DG can be seen as a possible solution to such a problem. An experimental feasibility study for a self-aligned double gate structure has been proposed [1]. In this present work, the work is being extended to produce sub 50 nm DG MOSFETs with Mo-gates to reduce gate depletion effects. Currently the feasibility of using such an approach for sub 50 nm DG structures is being investigated using a back-side illumination process on quartz substrates. After that, transistors will be fabricated using a similar approach. In parallel, simulation studies on device optimization are being pursued to optimize the circuit performance of DG MOSFETs.
The rapid growth of the semiconductor industry has been enabled by transistor scaling to improve the performance and cost of integrated circuit products. Continued scaling of the MOSFET presents new technological challenges as fundamental material and process limits are approached. It would therefore be useful to investigate novel FET structures that could be simpler to fabricate and more scalable than the MOSFET.
In this project we are focusing on the fabrication and characterization of short-channel (Lg < 20 nm) thin-body Schottky-gate transistors. The chief advantage of this structure compared to the conventional MOSFET lies in its extreme simplicity of structure and fabrication. The transistor has no p-n junctions between the S/D and channel, thus eliminating the requirement of hyper-abrupt junctions. The structure is constituted of a metal semiconductor contact as the front gate and a MOS back gate to adjust the threshold voltage. The conduction through the device is essentially resistive (similar to a JFET) with the resistance of the channel being adjusted using the front and back gate voltages. The channel lies in the middle of a thin silicon layer, thus making the interface quality unimportant for performance. In order to have channel pinch off at low gate voltages and good drive currents at high gate voltages of about 0.6 V (as desired for sub 10 nm devices), it is essential to have a heavily doped thin silicon channel, with the silicon thickness not very critical. Also, unlike the double gate MOSFET, the alignment between the front and back gates is not important for good transistor performance.
A metal-semiconductor contact typically suffers from (1) a large leakage current and, (2) Fermi level pinning. In order to overcome the two issues, an extremely thin layer (5-10 A) of silicon nitride is proposed to be used as a front gate dielectric. With conduction through the middle of the channel, the interface quality is not going to be very critical to the transistor performance. Simulations of this structure were done using the device simulator MEDICI and the results were compared to comparable double-gate MOSFET structures. The drive currents and short channel effects are comparable to the MOSFET, with the MESFET showing a better short channel performance. The drive current and transconductance are slightly poorer, but other benefits of the device are compelling enough to pursue the device further.
The fabrication of this structure has been started with the first run being tried on a poly-silicon channel to evaluate the feasibility of this idea. Later on, emphasis shall be given on thin silicon film crystallization to improve the transistor drive current. In the future we propose to demonstrate that this device can be scaled down far beyond the MOSFET limits and, theoretically, all the way to atomic dimensions. With a simple process flow and a poly-silicon channel, it is likely to be a good candidate for 3D intregration of devices as well.
The light-addressable potentiometric sensor (LAPS) is an ion-sensitive biosensor which can detect activity images of a group of cells [1]. The biggest disadvantage of the conventional LAPS structure is the low spatial resolution. The conventional LAPS composes three flat layers: silicon, silicon dioxide, and silicon nitride from bottom to top. The spatial resolution issue is generated by minority carrier diffusion in the silicon. The new design patterns the silicon layer to form discrete pillars of LAPS on a flat conductive and transparent layer. The pillars block the carrier diffusion, leading to a better spatial resolution decided by the size of pillars.
The goal of this project is to build a single cell activity detection system composed of a microfluidic system, a LAPS, and a signal detection system. The minority carrier diffusion model is used to investigate the spatial resolution limitation for conventional LAPS, and it is improved to fit experimental results. The diffusion model under the short-base assumption is being researched to predict the photocurrent value of LAPS pillars. Fabrication processing is being discussed, and the experiment system is being built at the same time.
Image enhancement and lateral size analysis tools are used to quantitatively examine roughness via scanning electron microscopy (SEM) and atomic force microscopy (AFM). The tools are then applied to study the effects of aerial image contrast and threshold set points (see Figure 1) upon LER and side edge roughness (SER) of several different DUV chemically amplified resists, using programmed double exposures with an ASML 248 nm wavelength stepper tool to create variable contrast levels. The threshold set point is defined as the minimum exposure dose necessary for resist development. Results show that in the case of Shipley's UV210, for instance, LER and SER do not increase significantly until aerial image contrast drops below around 38% (see Figure 2).
Advanced measurement and analysis techniques are used to yield a deeper understanding of and higher confidence in the data collected. AFM analysis of a sidewall yields two-dimensional information regarding that sidewall. Aside from merely mentioning SER values, the frequency and size of roughness are studied. In examining the data, roughness is typically seen as smooth, low rolling hills of about 20 nm peak:peak spacing and 1 nm height. The randomness of roughness can also be studied using this method, to help understand root causes or LER and SER.
SEM analysis itself falls prey to optical aberrations analogous to those seen in lithography. Astigmation, defocus, and other aberrations blur the micrograph, which is used to quantitatively assess LER. Even a system with no aberrations still has diffraction limited blurring. Deblurring the micrograph can improve image quality, therefore enhancing the accuracy of the LER data extracted from the SEM image. Deblurring is performed by iteratively solving for the point spread function (PSF) of the unknown blurring source and deconvolving the image with the PSF (see Figure 3). The LER does indeed change significantly. One example shows root mean square LER equal to 4.7 nm before image enhancement and 5.9 nm afterwards. Aside from improving the LER data, this technique also helps to determine the most significant aberrations seen in the SEM tool by analyzing the PSF used to deconvolve the image
Figure 1: Aerial image contrast variation at two different energy threshold set points
Figure 2: Effect of aerial image contrast upon SER at 0.3 intensity threshold set point
Figure 3: Deconvolving an SEM image with a calculated PSF in order to improve image quality and receive more accurate LER values
The focus of this research is the fabrication of light modulator nanomirror arrays with on-chip integrated circuits for static and dynamic device characterization. While conventional optical MEMS devices have features on the order of tens of microns, we wish to eventually fabricate light modulators with a reflective area of one sq. µm or less. The idea is to replace unwieldy and expensive masks with spatial light modulator arrays that promise to be more cost-effective and can eliminate the design-to-mask wait period.
Each mirror is modulated with an electrostatic force across a gap of around a few tenths of a micron. Damping is achieved by energy dissipation via a resistor built into the flexure hinge. The schematic diagram of a parallel-plate mirror design is shown in Figure 1. The mirrors tilt when a potential difference is applied between the underlying poly electrode and the mirror. The modulation tilt angle is limited to 1 or 2 degrees from bias position.
We have completed preliminary analysis of heat dissipation and static behavior of the mirror earlier in the project. Fabrication of a parallel-plate structure with sacrificial gap ~ 100 nm and mirror area ranging from 1x1 µm2 to 5x5 µm2 is complete. A recently fabricated mirror device is shown in Figure 2. The current focus of our research is on optical measurement of device properties and IC design for eventual on-chip characterization.
Pure phase modulation (using normal motion of the mirrors) and phase/amplitude modulation (using tilting motion of the mirrors) methods of pattern generation are studied using analytical methods and simulators such as (far-field) SPLAT and (near-field) TEMPEST. The objective is to quantify aerial image in terms of important parameters such as normalized image log slope, contrast, and spots/min feature size, to come up with the most robust method of gray-scaled pattern generation using analog modulation of micromirrors.
Figure 1: Schematic diagram of a parallel-plate micromirror
Figure 2: SEM view of a 5 x 5 µm2 mirror
Solution-based fabrication promises to be an inexpensive and effective means of producing integrated circuits on flexible substrates for a variety of applications, since it will allow the use of ultra low cost printing-based fabrication methods. In order to develop a successful solution-based manufacturing technology, we need access to materials analogous to soluble conductors, dielectrics, and semiconductors. In this project, we are developing a library of such materials, and applying them to various device and circuit architectures. Conductors are a necessary element for device contacts, interconnects, capacitor plates, and inductive elements. We form highly conductive films from solutions that can be deposited on a variety of materials. In order to achieve this we have taken advantage of the low anneal temperatures associated with nano-crystals. We have already developed ink-jet printable gold nano-crystals that, upon anneal at 120 C, result in extremely low-resistance conductive films. We have also developed novel syntheses for silver and copper nano-crystals to be used in similar applications.
Development of suitable dielectrics is another key challenge to the solution-based manufacturing of devices and circuits. Both high-K and low-K dielectrics are needed for device gating and passivation respectively. We are currently developing novel, solution-based materials for the formation of Hafnium, Zirconium, Titanium, and Aluminum oxides as high-K dielectrics, and polyimide-based passivation dielectrics.
The development of a soluble high-performance semiconducting material is perhaps one of the greatest challenges facing the solution-based manufacturing of circuits. Prompted by recent efforts in the field, we are exploring the development of a soluble precursor of pentacene [1]. This modified pentacene molecule is soluble in a variety of solvents, and efficiently converts to pentacene, itself, upon mild heating. We have already manufactured organic FETs using these molecules and are in the process of further enhancing this technology.
Organic transistors show marked sensitivity to chemical compounds over their silicon counterparts. While in the past this may have been regarded as a disadvantage, it is possible to leverage this response by designing chemical sensors based on organic TFTs. Since it is has been shown that transistor drain currents are affected by exposure to various chemical analytes [1], it is possible to design an array of TFTs that would register unique signatures to different chemical agents and gases.
In this work, we are interested in designing chemical sensors capable of positively identifying a specific chemical agent or gas as well as an integrated approach to fabricating these devices. The development of these sensors will occur in several areas including materials, fabrication, and systems design. It involves understanding the responses of the active materials to an assortment of analytes and tailoring their chemistry to attenuate these responses. For a fully integrated approach, it is also necessary to develop the supporting circuitry, derived from organic materials, which would integrate the sensors’ responses and provide electrical readout. Finally, a solution-based process that is compatible with our in-house inkjet technology will augment functionality by integration into areas such as cloth or food packaging.
While organic semiconducting materials show promise in the realm of low cost/large area applications, the performance of these materials remains low when compared to that of traditional inorganic semiconductors. Certain approaches, however, may improve characteristics such as the field-effect mobility exhibited by current organic semiconductors.
This work seeks to improve the performance of organic semiconducting devices with various techniques, through both device design and organic synthesis. Device scaling is to be utilized to study nanometer scaled organic devices in order to investigate transport mechanisms. Synthetic chemistry will then be attempted to create devices with increased molecular ordering and functionalized integration. Overall this project seeks to drive toward molecularly scaled organic FETs utilizing principles of self-assembly and material integration.
Conventional ICs still suffer from certain incremental costs and are limited to silicon substrates, thereby preventing them from becoming more ubiquitous in consumer applications. Organic-based semiconductors have the advantage of being processed in solution allowing for them to be sprayed or dispensed on a plethora of compatible substrates, including paper, plastic, cloth, and glass. While many organic semiconductors so far do not exhibit the same performance as their silicon counterparts, the advantage of solution-based processing can save costs and allow for widespread integration, making them ideal materials for low-cost electronics.
In this work, we are developing the technology to make ASICs for a variety of innovative and integrated applications. Specifically, the work incorporates several areas of development: (1) the inkjet technology for dispensing and patterning the necessary materials; (2) organic-based molecules for the semiconducting material; (3) advanced materials such as nanocrystals to be used for interconnects and dielectrics; and (4) an integrated, additive process that is also substrate tolerant. We have made progress in multiple areas and are developing a fully integrated process for active devices. Such a process would be used to fabricate RF ID tags, chemical sensors, transducers, or displays on flexible and novel substrates, such as plastic or cloth.
Superconducting niobium integrated circuit technology employing Josphson tunnel junctions is well established, reliable, and reproducible. It has been used to make circuits with 70,000 junctions on a chip and has the potential for making single flux quantum (SFQ) circuits that operate at 50 GHz and above with extremely low power dissipation. However, it is not the ideal technology for these circuits, since the tunnel junctions must be shunted with resistors to yield the needed I-V characteristics. The goal of this project is to provide a replacement for the tunnel junction and its shunt resistor in the form of an internally shunted Josephson junction. The elimination of the external shunt not only saves space, but also avoids steps in the fabrication process and minimizes parasitic inductances that complicate circuit design and are detrimental to performance.
We are working in collaboration with a group at Arizona State University to form Josephson junctions by subtractive etching of the so-called “pentalayers.” A pentalayer covers an entire 4” silicon wafer and has the thin film form Nb/NbTiN/TaN/NbTiN/Nb, in which the TaN layer is the junction barrier. In varying the nitrogen content in TaN, the resistivity passes through the metal-insulator transition. By judicious choice of barrier thickness and resistivity, we can control the junction current density and shape of its I-V characteristic.
The experimental results are extremely encouraging. The I-V characteristics show a typical resistively shunted junction behavior. Critical current density of about 20 kA/cm2 has been obtained. This value is close to the desired critical current density for niobium-based junctions. Also, the correlation between the barrier resistance and the critical current has been observed. A parameter that determines the upper speed of superconducting SFQ digital circuit is the product (IcR) of the maximum zero-voltage current Ic and junction resistance R in the absence of supercurrent. We have obtained IcR products that will allow circuit operation at over 100 GHz and are quite similar to junction with such ideal properties. Our current effort is focused on optimizing the deposition parameters of barrier TaN and improving the reproducibility of junctions. The next step will be directed toward demonstrating various circuits using this new technology.
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Superconducting devices have a very high operation speed (up to a few hundred GHz) and extremely low power dissipation, which are essential for ultra-high-speed computing and telecommunication applications. High switch speed requires high Jc (critical current density) of 10-20 kA/cm2 and small junction area (1 mm2 or less). Most current superconducting junction and IC fabrication is still based on 2-3 mm technologies. It is important for high-speed superconducting digital applications to develop a suitable technology for micron and submicron junction and IC fabrication. When the junction areas approach micron and submicron sizes, the fabrication becomes more difficult. For 1 mm2 junction, the via through the dielectric layer to contact the junction would have to be 0.6 mm2 or less. This would require advanced photolithography tools to increase resolution and alignment accuracy. It also demands better dry-etch profile control. One common approach is to use CMP to remove the covering dielectric layer and expose the underlying metal contact. But CMP complicates the process and increases the cost. We have developed a new approach for high critical current density (Jc) small junction fabrication. The key step is light anodization that forms a thin double-layer of Al2O3/Nb2O5 oxides around the junction area and on the sidewalls of the junction. This anodization ring is a good dry-etch stop, so the via for the junction contact can be larger than the junction area. The anodization ring can also protect the junction from plasma damage during dry etching and sputtering steps, therefore, it can reduce the junction leakage current and critical-current spread. The new technique is very simple and cost effective compared with the CMP approach. It needs only one additional mask and process step. We have used the technique to fabricate high-Jc submicron Nb/Al-AlOx/Nb tunnel junctions with very low critical-current spreads. The smallest junction area is 0.3 mm2. The critical current densities are up to 20 kA/cm2. Using this technique, we have also fabricated Nb SQUIDs and various Nb digital ICs. MIT Lincoln Laboratory, Hypres, and TRW have successfully adopted the new technique in their superconducting IC processes.
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