Planar Self-Aligned Double Gate Sub 50 nm MOSFETs

Double-gate (DG) MOSFETs are a proposed solution to extended CMOS scaling beyond bulk-Si MOSFETs. A variety of DG structures have been proposed [1]. Vertical structures, such as the FinFET have a layout penalty related to the routing of wires to both the gates. A planar DG can be seen as a possible solution to such a problem. An experimental feasibility study for a self-aligned double gate structure has been proposed [1]. In this present work, the work is being extended to produce sub 50 nm DG MOSFETs with Mo-gates to reduce gate depletion effects. Currently the feasibility of using such an approach for sub 50 nm DG structures is being investigated using a back-side illumination process on quartz substrates. After that, transistors will be fabricated using a similar approach. In parallel, simulation studies on device optimization are being pursued to optimize the circuit performance of DG MOSFETs.

[1]

D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, "A Folded-Channel MOSFET for Deep-Sub-Tenth Micron Era," Int. Electron Devices Mtg. Technical Digest, San Francisco, CA, December 1998.

[2]

B. E. Roberds, E. J. Whang, A. Rudolph, and B. S. Boyle, "Investigation of a Novel-Self-Aligned Dual Gate MOSFET Structure," IEEE Int. SOI Conf., Stuart, FL, October 1998.