Tsize is a transistor sizer for combinational static CMOS circuits. It reads in a flat netlist file, a process technology file, and a file describing I/O timing specifications. The program produces a sized netlist file summarizing the delay information.
Based on the "distributed RC delay model" of Penfield-Rubinstein, Tsize adjusts the transistor sizes of the circuit to meet the timing constraints with the minimum total active area. By default, the program uses a heuristic algorithm to size the circuit. The user may also request an additional optimization procedure, based on nonlinear programming, to fine-tune the result.
Documentation Included with the Program:
- J.-M. Shyu, Performance Optimization of Integrated Circuits (UCB/ERL M88/74, November 1988). Available separately for $10.00
Foreign Distribution: Yes