SWEC performs fast and accurate transient analyses of digital Metal-Oxide-Semiconductor (MOS) integrated circuits, with or without lossy interconnects. The program uses the Stepwise Equivalent Conductance Integration approach, the event-driven approach, and the recursive convolution simulation of lossy interconnects. This combination greatly improves the computational efficiency for transient simulation. SWEC can produce results of the same accuracy as SPICE3, and is one to two orders-of-magnitudes faster.
Documentation included with the tape:
- Example test circuits.
- SWEC Version 2.4 User's Guide. Available separately for $2.50.
Additional Documentation Available:
- S. Lin, Circuit Simulation for VLSI and Electronic Packaging Design (UCB/ERL M95/80, October 1995). $7.50
- S. Lin and E. S. Kuh, "Transient Simulation of Lossy Interconnects Based on the Recursive Convolution Formulation," IEEE Trans. Circuits and Systems, Vol. 39, No. 11, pp. 879-892, November 1991. $7.50
- S. Lin, E. S. Kuh, and M. Marek-Sadowska, "Stepwise Equivalent Conductance Circuit Simulation Technique," IEEE Trans. Computer-Aided Design, Vol. 12, No. 5, pp. 672-683, May 1993. $7.50
- S. Lin, M. Marek-Sadowska, and E. Kuh, "SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits," Proc. European Design Automation Conf., pp. 142-148, February 1991. $5.00
- S. Lin and E. Kuh, "Transient Simulation of Lossy Interconnect," Proc. 29th Design Automation Conf., pp. 81-86, June 1992. $5.00
- P. Buch, S. Lin, V. Nagasamy, and E. Kuh, "Techniques for fast Circuit Simulation Applied to Power Estimation of CMOS Circuits," Proc. Int. Symp. Low Power Design, pp. 135-138, April 1995. $5.00
Special Licensing/Distribution Restrictions: We ask that you send a letter stating that you will not give or sell the program to anyone outside your organization.
Foreign Distribution: Yes