CIDER is a mixed-level circuit and device simulator that provides a direct link between technology parameters and circuit performance. In cases where compact semiconductor device models are inaccurate or nonexistent, a mixed-level circuit and device simulator can provide greater accuracy by numerically modeling the critical devices in a circuit. Compact models can be used for the noncritical devices. A tool such as CIDER can be useful in the development of new process technologies and device designs, improved compact models, ASIC standard cell libraries, and critical subcircuits of full-custom ICs.
CIDER couples the latest version of SPICE3 (version 3F4) to an internal C-based device simulator, DSIM. SPICE3 provides circuit analyses, compact models for semiconductor devices, and an interactive user interface. DSIM provides accurate, one- and two-dimensional numerical device models based on the solution of Poisson's equation, and the electron and hole current-continuity equations. DSIM incorporates many of the same basic physical models found in the the Stanford two-dimensional device simulator PISCES. Input to CIDER consists of a SPICE-like description of the circuit and its compact models, and PISCES-like descriptions of the structures of numerically modeled devices. As a result, CIDER should seem familiar to designers already accustomed to these two tools. For example, SPICE3F4 input files should run without modification, producing identical results.
CIDER is based on the mixed-level circuit and device simulator CODECS, and is a replacement for this program. The basic algorithms of the two programs are the same. Some of the differences between CIDER and CODECS are described below. The CIDER input format has greater flexibility and allows increased access to physical model parameters. New physical models have been added to allow simulation of state-of-the-art devices. These include transverse field mobility degradation, important in scaled-down MOSFETs, and a polysilicon model for poly-emitter bipolar transistors. Temperature dependence has been included over the range from -55°C to 125°C. The numerical models can be used to simulate all the basic types of semiconductor devices: resistors, MOS capacitors, diodes, BJTs, JFETs and MOSFETs. BJTs and JFETs can be modeled with or without a substrate contact. Support has been added for the capture of device internal states. Post-processing of device states can be performed using the NUTMEG user interface of SPICE3. Previously computed states can be loaded into the program to provide accurate initial guesses for subsequent analyses. Finally, numerous small bugs have been discovered and fixed, and the program has been ported to a wider variety of computing platforms.
The current version of CIDER supports execution across a network of workstations using distributed processing techniques. Parallel model evaluation assigns different numerically modeled devices to different processors, thereby spreading the dominant computational workload across the network. All necessary support software is provided in the distribution. This includes a specially modified version of SPICE3 and the TCGMSG message passing library developed at Argonne National Laboratory. Compile-time options allow both serial and parallel versions of the CIDER executable to be obtained. While basic features of CIDER have been tested in the parallel version, some less used features may not work properly in the parallel version.
Berkeley tradition calls for the naming of new versions of programs by affixing a (number, letter, number) triplet to the end of the program name. Under this scheme, CIDER should instead be named CODECS2A.1. However, tradition has been broken in this case because major incompatibilities exist between the two programs and because it was observed that the acronym CODECS is already used in the analog design community to refer to coder-decoder circuits.
Documentation Included with the Program:
- CIDER User's Guide. Available separately for $5.00
Additional Documentation Available:
- K. Mayaram, CODECS: A Mixed-Level Circuit and Device Simulator (UCB/ERL M88/71, November 1988). $15.00
- D. Gates, An Inversion-Layer Mobility Model for CODECS (UCB/ERL M90/96, October 1990). $10.00
- D. Gates, Design-Oriented Mixed-Level Circuit and Device Simulation (UCB/ERL M93/51, June 1993). $15.00
Foreign Distribution: Yes