Berkeley EECS Annual Research Symposium
Electrical Engineering and Computer Science College of Engineering UC Berkeley

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BEARS 2005
BEARS 2004

Gigascale Systems Research Center (GSRC)
3:00-5:00pm, 2108 Alston Way, Suite 200

The University of California at Berkeley is the lead university for this focus center, the Gigascale Systems Research Center (GSRC), with Professor Jan Rabaey as the center's director.

The center's research agenda focuses on pertinent problems the semiconductor industry faces in the next decade in the areas of system design, integration, test and verification. To sustain current growth, the industry requires orders of magnitude of improvement in energy efficiency, cost, reliability and time-to-market.

To address the multiple challenges within this focus, the center is structured along eight interlocking research themes, each led by a theme leader. The horizontal themes, Heterogeneous System Design & Integration and Soft Systems, represent two visions on how integrated systems are to be realized. These horizontal themes are combined with four vertical ones, each of which addresses one particular aspect of embedded integrated system design. The Power-Aware Systems, Reliable Systems, System Verification and Embedded Self-Test themes, respectively, address the power and energy, reliability, verification and test roadblocks that are looming on the horizon.

Finally, the System-Level Living Roadmap provides an environment to explore how the different cost metrics of design will evolve in the next decade, taking a system-level view. This high-level perspective is unique and complements and builds on top of the existing roadmapping efforts. This effort, which encompasses and integrates all the research activities of the center, is essential in identifying emerging challenges and in steering the research evolution of the center.

Please join our Open House in conjunction with BWRC

GSRC Overview Electronic systems design in the late- and post-silicon age

With semiconductor technology reaching the nanometer scale in approximately 15 years, concerns such as complexity, power, variability and reliability are forcing major shifts in design paradigms. More specifically, we see the following major trends:
* Massively parallel, programmable architectures will make major inroads in integrated circuits for both computational infrastructure and peripheral devices, inspired by power and time-to-market concerns.
* The challenges of parameter variability and circuit reliability are best addressed by allocating an increasing number of transistors to the tasks of dynamic on-line tuning and providing error-resiliency. Ultimately, it probably will lead to computational models that are substantially different from those that are in vogue today.
* Each of the above strategies addresses a particular problem, such as power, concurrency, variability or reliability, and integrates aspects from multiple communities (such as modeling, exploration, synthesis, verification, and test). To do this successfully requires a common design technology framework for complex heterogeneous systems which can be shared over technology domains and optimization targets.

Addressing these challenges requires innovative and disruptive solutions. By bringing the best minds in US academia (41 faculty from 17 institutions) together in a collaborative and forward-looking setting, the GSRC is uniquely positioned to deliver some of the answers.

Jan Rabaey, Sharad Malik and Ken Lutz, Center Directors

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