Katherine A. Yelick
Kathy Yelick received her Bachelors, Masters, and Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology, 1985, 1985, 1991, respectively.
- K. A. Yelick, P. N. Hilfinger, S. L. Graham, D. Bonachea, J. Su, A. Kami, K. Datta, P. Colella, and T. Wen, "Parallel languages and compilers: Perspective from the Titanium experience," Intl. J. High Performance Computing Applications, vol. 21, no. 3, pp. 266-290, 2007.
- E. Givelberg and K. A. Yelick, "Distributed immersed boundary simulations in Titanium," SIAM J. on Scientific Computing, vol. 28, no. 4, pp. 1361-1378, July 2006.
- S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, and K. A. Yelick, "The potential of the Cell processor for scientific computing," in Proc. 3rd Conf. on Computing Frontiers, New York, NY: ACM Press, 2006, pp. 9-20.
- C. Bell, D. Bonachea, R. Nishtala, and K. A. Yelick, "Optimizing bandwidth limited problems using one-sided communication and overlap," in Proc. 20th Intl. Parallel and Distributed Processing Symp., Piscataway, NJ: IEEE Press, 2006, pp. 10 pp..
- K. A. Yelick and J. Demmel, "OSKI -- Optimized Sparse Kernel Interface," 2006.
- E. Givelberg and K. A. Yelick, "IB Using Titanium," 2005.
- A. Kamil, J. Su, and K. A. Yelick, "Making sequential consistency practical in Titanium," in Proc. 2005 ACM/IEEE Supercomputing Conf., Los Alamitos, CA: IEEE Computer Society Press, 2005, pp. 15 pp..
- T. El-Ghazawi, W. Carlson, T. Sterling, and K. A. Yelick, UPC: Distributed Shared-Memory Programming, Wiley-Interscience, Hoboken, NJ: Wiley, 2005.
- A. W. Trivelpiece, R. Biswas, J. Dongarra, P. Paul, and K. A. Yelick, Assessment of High-End Computing Research and Development in Japan: Final Report, Baltimore, MD: World Technology Evaluation Center, Inc., 2004.
- B. C. Lee, R. W. Vuduc, J. Demmel, and K. A. Yelick, "Performance models for evaluation and automatic tuning of symmetric sparse matrix-vector multiply (Best Paper Prize)," in Proc. 2004 Intl. Conf. on Parallel Processing (ICPP 2004), R. Eigenmann, Ed., Vol. 1, Los Alamitos, CA: IEEE Computer Society, 2004, pp. 169-176.
- W. Chen, D. Bonachea, J. Duell, P. Husbands, C. Iancu, and K. A. Yelick, "A performance analysis of the Berkeley UPC compiler," in Proc. 17th Annual Intl. Conf. on Supercomputing, New York, NY: ACM Press, 2003, pp. 63-73.
- W. Chen, D. Bonachea, J. Duell, P. Husbands, C. Iancu, K. A. Yelick, and D. E. Culler, "The Berkeley UPC Compiler," 2003.
- B. R. Gaeke, P. Husbands, X. S. Li, L. Oliker, K. A. Yelick, and R. Biswas, "Memory-intensive benchmarks: IRAM vs. cache-based machines," in Proc. 16th Intl. Parallel and Distributed Processing Symp., Piscataway, NJ: IEEE Press, 2002, pp. 30-36.