Costas J. Spanos
COSTAS J. SPANOS received the Electrical Engineering Diploma from the National Technical University of Athens, Greece in 1980 and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Carnegie Mellon University in 1981 and 1985, respectively. From 1985 to 1988 he was with the advanced Computer-Aided Design group of Digital Equipment Corporation, where he worked on the statistical characterization, simulation and diagnosis of VLSI processes.
In 1988 he joined the faculty in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. He was the Director of the Berkeley Microfabrication Laboratory from 1994 to 2000, the Director of the Electronics Research Laboratory from 2004 to 2005, and the Associate Dean for Research in the College of Engineering from 2004 to 2008. From 2008 to 2010 he served as Associate Chair for the EECS Department, and from 2010 through June 2012, he was the Chair of the Department.
Professor Spanos has served in the technical committees of numerous conferences and was the editor of the IEEE Transactions on Semiconductor Manufacturing from 1991 to 1994. He has published more than 200 refereed articles, has received several best paper awards and has co-authored a textbook on semiconductor manufacturing. His present research interests include the application of statistical analysis in the design and fabrication of integrated circuits, and the development and deployment of novel sensors and computer-aided techniques in semiconductor manufacturing. In 2000, he was elected Fellow of the Institute of Electrical and Electronic Engineers for contributions and leadership in semiconductor manufacturing.
- Y. Qiao, K. Qian, and C. J. Spanos, "Variability aware compact model characterization for statistical circuit design optimization," in Proceedings of SPIE, Vol. 8327, 2012, pp. 83270J.
- G. S. May and C. J. Spanos, Fundamentals of Semiconductor Manufacturing and Process Control, Wiley-Interscience, Hoboken, NJ: John Wiley & Sons, Inc./IEEE Press, 2006.
- K. Poolla and C. J. Spanos, "Methods of and apparatus for controlling process profiles," U.S. Patent 7,016,754. March 2006.
- Q. Zhang, P. Friedberg, K. Poolla, and C. J. Spanos, "Enhanced spatial PEB uniformity through a novel bake plate design," in Proc. AEC/APC XVII Symp. 2005, Austin, TX: AEC/APC Official Proceedings CD-ROM, 2005, pp. 1-5.
- M. Freed, M. V. P. Kruger, C. J. Spanos, and K. Poolla, "Wafer-grown heat flux sensor arrays for plasma etch processes," IEEE Trans. Semiconductor Manufacturing, vol. 18, no. 1, pp. 148-162, Feb. 2005.
- M. L. Freed, R. S. Mundt, and C. J. Spanos, "Methods and apparatus for obtaining data for process operation, optimization, monitoring, and control," U.S. Patent 6,691,068. Feb. 2004.
- M. Freed, M. Kruger, C. J. Spanos, and K. Poolla, "Autonomous on-wafer sensors for process modeling, diagnosis, and control," IEEE Trans. Semiconductor Manufacturing, vol. 14, no. 3, pp. 255-264, Aug. 2001.
- X. Niu, N. Jakatdar, J. Bao, and C. J. Spanos, "Specular spectroscopic scatterometry," IEEE Trans. Semiconductor Manufacturing, vol. 14, no. 2, pp. 97-111, May 2001.