Kurt Keutzer

Professor

Research Areas

• Computer Architecture & Engineering (ARC)
• Design of Electronic Systems (DES)

Research Centers

• Berkeley Center for New Media (BCNM)
• Berkeley Wireless Research Center (BWRC)
• Center for Hybrid and Embedded Software Systems (CHESS)
• Donald O. Pederson Center for Electronics Systems Design (DOP)
• Gigascale Systems Research Center (GSRC)

Teaching Schedule (Spring 2008)

• CS 294-27. Architecting Parallel Software w/ the Thirteen Dwarfs, Tu 10:00-1:00P, 540AB Cory

Biography

He received his B.S. degree in Mathematics from Maharishi International University, 1978 and his M.S. and Ph.D. degrees in Computer Science from Indiana University, 1981 and 1984 respectively.

In 1984 Kurt joined AT&T Bell Laboratories applying various computer-science disciplines to practical problems in computer-aided design. In 1991 Kurt joined Synopsys, Inc., continuing his research and culminating in his position as CTO and Senior Vice-President of Research. Kurt left Synopsys in January 1998 to become Professor of Electrical Engineering and Computer Science at the UC Berkeley. From 1998 until 2002 he served as the Associate Director of the Gigascale Silicon Research Center (GSRC). The GSRC currently funds over thirty faculty and dozens of graduate students across a dozen academic institutions. Kurt has researched a wide number of areas related to synthesis and high-level design and his research efforts have led to three Design Automation Conference (DAC) Best Paper Awards, a Distinguished Paper Citation from the International Conference on Computer-Aided Design (ICCAD) and a Best Paper Award at the International Conference in Computer Design (ICCD). He co-authored the book entitled Logic Synthesis published by McGraw-Hill in 1994 and the book entitled Closing the Gap Between ASIC and Custom , currently a best-seller. Currently he serves on editorial boards of three journals: Integration - the VLSI Journal; Design Automation of Embedded Systems and Formal Methods in System Design. He is currently a consultant to Cadence Design and serves on the Technical Advisory Boards of 0-in Design Automation, Catalytic Inc., Co-Ware, Reshape, Stretch Inc., and Tensilica. He has also been active private investor, investing in 0-in Design Automation, Cadabra (acquired by Numerical Technologies), Catalytic, Everest Design Automation (acquired by Synopsys), Right-Track CAD (acquired by Altera), Stretch, and Tensilica. Kurt is a Fellow of the IEEE.

Selected Publications

• J. Chong, N. R. Satish, B. C. Catanzaro, K. Ravindran, and K. Keutzer, "Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling," in ICME, 2007.
• N. R. Satish, K. Ravindran, and K. Keutzer, "A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors," in 10th Conference of Design, Automation and Test in Europe (DATE), 2007, pp. 57-62.
• Y. Jin, N. R. Satish, K. Ravindran, and K. Keutzer, "An Automated Exploration Framework for FPGA-based Soft Multiprocessor Systems," in Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES), ACM Press, 2005, pp. 273-278.
• K. Ravindran, N. R. Satish, Y. Jin, and K. Keutzer, "An FPGA-based Soft Multiprocessor for IPv4 Packet Forwarding," in 15th International Conferenece on Field Programmable Logic and Applications (FPL), 2005, pp. 487-492.
• D. Chinnery and K. Keutzer, Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Boston, MA: Kluwer Academic Publishers, 2002.
• K. Keutzer, S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Invited Paper: System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
• D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in 1998 IEEE/ACM Intl. Conf. on Computer-Aided Design. Digest of Technical Papers, New York, NY: ACM, 1998, pp. 203-11.
• S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang, "Storage assignment to decrease code size," SIGPLAN Notices, vol. 30, no. 6, pp. 186-195, June 1995.
• A. Ghosh, S. Devadas, K. Keutzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," in Proc. 29th ACM/IEEE Conf. on Design Automation, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 253-259.
• K. Keutzer, "DAGON: Technology binding and local optimization by DAG matching," in Proc. 24th ACM/IEEE Conf. on Design Automation, Piscataway, NJ: IEEE, 1987, pp. 341-347.