Kurt Keutzer

Professor

Research Areas

• Computer Architecture & Engineering (ARC)
• Design, Modeling and Analysis (DMA)

Research Centers

• Berkeley Center for New Media (BCNM)
• Donald O. Pederson Center for Electronics Systems Design (DOP)
• Gigascale Systems Research Center (GSRC)
• Parallel Computing Laboratory (ParLab)

Biography

He received his B.S. degree in Mathematics from Maharishi International University, 1978 and his M.S. and Ph.D. degrees in Computer Science from Indiana University, 1981 and 1984 respectively.

In 1984 Kurt joined AT&T Bell Laboratories applying various computer-science disciplines to practical problems in computer-aided design. In 1991, Kurt joined Synopsys, Inc., continuing his research, culminating in his position as CTO and Senior Vice-President of Research. Kurt left Synopsys in January 1998 to become a Professor of Electrical Engineering and Computer Sciences at UC Berkeley. From 1998 through 2002, he served as the Associate Director of the Gigascale Silicon Research Center (GSRC). The GSRC currently funds over thirty faculty and dozens of graduate students across a dozen academic institutions.

Kurt has researched a wide number of areas related to synthesis and high-level design and his research efforts have led to three Design Automation Conference (DAC) Best Paper Awards, a Distinguished Paper Citation from the International Conference on Computer-Aided Design (ICCAD) and a Best Paper Award at the International Conference in Computer Design (ICCD). He co-authored the book entitled Logic Synthesis published by McGraw-Hill in 1994 and the book entitled Closing the Gap Between ASIC and Custom, which was a best-seller.

Currently he serves on the editorial boards of three journals: Integration - the VLSI Journal; Design Automation of Embedded Systems and Formal Methods in System Design. Kurt has served on the technical program committees of DAC, ICCAD and ICCD as well as the technical and executive committees of numerous other conferences and workshops. He is a Fellow of the IEEE.

Selected Publications

• M. Anderson, B. Catanzaro, J. Chong, E. Gonina, K. Keutzer, C. Lai, M. W. Moskewicz, M. Murphy, B. Su, and K. Keutzer, "PALLAS: Mapping Applications onto Manycore," in Multiprocessor System-on-Chip: Hardware Design and Tool Integration, Springer, 2010, pp. 89-114.
• J. Chong, E. Gonina, K. You, and K. Keutzer, "Exploring Recognition Network Representations for Efficient Speech Inference on Highly Parallel Platforms," in Proceedings of the 11th Annual Conference of the International Speech Communication Association, 2010, pp. 1489-1492.
• D. Kolossa, J. Chong, S. Zeiler, and K. Keutzer, "Efficient Manycore CHMM Speech Recognition for Audiovisual and Multistream Data," in Proceedings of the 11th Annual Conference of the International Speech Communication Association, 2010, pp. 2698-2701.
• J. Chong, E. Gonina, and K. Keutzer, "Monte Carlo Methods," in 2nd Annual Conference on Parallel Programming Patterns (ParaPLoP'10), 2010.
• M. Dixon, J. Chong, and K. Keutzer, "Acceleration of Market Value-at-Risk Estimation," in Proceedings of the 2nd Workshop on High Performance Computational Finance, WHPCF '09, New York, NY, USA: ACM, 2009, pp. 5:1--5:8.
• K. You, J. Chong, Y. Yi, E. Gonina, C. Hughes, Y. Chen, W. Sung, and K. Keutzer, "Parallel Scalability in Speech Recognition: Inference engine in large vocabulary continuous speech recognition," IEEE Signal Processing Magazine, vol. 26, no. 6, pp. 124-135, Nov. 2009.
• J. Chong, E. Gonina, Y. Yi, and K. Keutzer, "A Fully Data Parallel WFST-based Large Vocabulary Continuous Speech Recognition on a Graphics Processing Unit," in Proceedings of the 10th Annual Conference of the International Speech Communication Association (InterSpeech), 2009, pp. 1183–1186.
• J. Chong, E. Gonina, Y. Yi, and K. Keutzer, "A Fully Data Parallel WFST-based Large Vocabulary Continuous Speech Recognition on a Graphics Processing Unit," in Proceedings of the 10th Annual Conference of the International Speech Communication Association (InterSpeech), 2009, pp. 1183–1186.
• J. Chong, Y. Yi, A. Faria, N. Satish, and K. Keutzer, "Data-Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processors," in Proceedings of the 1st Annual Workshop on Emerging Applications and Many Core Architecture, 2008, pp. 23-35.
• J. Chong, Y. Yi, A. Faria, N. Satish, and K. Keutzer, "Data-Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processors," in Proceedings of the 1st Annual Workshop on Emerging Applications and Many Core Architecture (EAMA), 2008, pp. 23--35.
• J. Chong, N. R. Satish, B. C. Catanzaro, K. Ravindran, and K. Keutzer, "Efficient parallelization of H.264 decoding with macro block level scheduling," in Proc. 2007 Intl. Conf. on Multimedia and Expo (ICME 2007), Piscataway, NJ: IEEE Press, 2007, pp. 1874-1877.
• Y. Jin, N. R. Satish, K. Ravindran, and K. Keutzer, "An Automated Exploration Framework for FPGA-based Soft Multiprocessor Systems," in Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES), ACM Press, 2005, pp. 273-278.
• K. Ravindran, N. R. Satish, Y. Jin, and K. Keutzer, "An FPGA-based Soft Multiprocessor for IPv4 Packet Forwarding," in 15th International Conferenece on Field Programmable Logic and Applications (FPL), 2005, pp. 487-492.
• D. Chinnery and K. Keutzer, Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Boston, MA: Kluwer Academic Publishers, 2002.
• K. Keutzer, S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Invited Paper: System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
• D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in 1998 IEEE/ACM Intl. Conf. on Computer-Aided Design. Digest of Technical Papers, New York, NY: ACM, 1998, pp. 203-11.
• S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang, "Storage assignment to decrease code size," SIGPLAN Notices, vol. 30, no. 6, pp. 186-195, June 1995.
• A. Ghosh, S. Devadas, K. Keutzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," in Proc. 29th ACM/IEEE Conf. on Design Automation, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 253-259.
• K. Keutzer, "DAGON: Technology binding and local optimization by DAG matching," in Proc. 24th ACM/IEEE Conf. on Design Automation, Piscataway, NJ: IEEE, 1987, pp. 341-347.