Chenming Hu

Professor

Research Areas

• Technology of solid-state devices

Research Centers

• Integrated Modeling Process and Computation for Technology (IMPACT)
• Microfabrication Lab (Microlab)

Teaching Schedule (Spring 2008)

• EE 130. Integrated-Circuit Devices, TT 12:30-2p, 521 Cory
• EE 298-12. Group Studies, Seminars, or Group Research, F 1-2P, 521 Cory

Biography

He received his B.S. degree from National Taiwan University and M.S. and Ph.D. degrees from the University of California, Berkeley, all in electrical engineering.

In 1997, Dr. Hu received the IEEE Jack A. Morton Award for contributions to MOSFET reliability physics. In 1999, he received the DARPA Most Significant Technological Accomplishment Award for co-developing FinFET. FinFET is a promising future MOSFET structure and has allowed several corporations and UC Berkeley to reset the world record of the smallest transistor several times down to 5nm gate length. In 2002, he received the IEEE Solid State Circuits Award for the BSIM transistor model. BSIM is the industry standard for IC simulation and is used in the design of most of the world's ICs with a cumulative value of over a hundred billion dollars. He has also received UC Berkeley's highest honor for teaching -- the Berkeley Distinguished Teaching Award.

He has authored or co-authored three books and 800 research papers and has supervised 60 doctoral students in the field of semiconductor technology. Dr. Hu is a member of the US National Academy of Engineering and Academia Sinica; a fellow of the IEEE and the Institute of Physics; and an Honorary Professor of the Chinese Academy of Science Microelectronics Institute, and National Chiao Tung University.

Selected Publications

• M. V. Dunga, C. Lin, X. Xi, D. Lu, A. Niknejad, and C. Hu, "Modeling Advanced FET Technology in a Compact Model," IEEE Transactions on Electronic Devices, vol. 53, pp. 1971-1978, Sep. 2006.
• A. Niknejad, M. V. Dunga, B. Heydari, H. Wan, C. Lin, S. Emami Neyestanak, C. Doan, X. Xi, J. He, and C. Hu, "Challenges in compact modeling for RF and microwave applications," in Workshop on Compact Modeling, 2005, pp. N/A.
• J. He, J. Xi, M. Chan, H. Wan, M. V. Dunga, B. Heydari, A. Niknejad, and C. Hu, "Charge-based core and the model architecture of BSIM5," in Quality of Electronic Design, 2005, pp. 96-101.
• A. Niknejad, C. Doan, S. Emami Neyestanak, M. V. Dunga, X. Xi, J. He, R. W. Brodersen, and C. Hu, "Next generation CMOS compact mofels for RF and microwave applications (Invited)," in RFIC Digest of Papers, 2005, pp. 141-144.
• X. Xi, J. He, M. V. Dunga, C. Lin, B. Heydari, H. Wan, M. Chan, A. Niknejad, and C. Hu, "The next generation BSIM for sun-100nm mixed-signal circuit simulation," in Proceedings of CICC, 2004, pp. 13-16.
• M. Chan, C. Lin, J. He, Y. Taur, A. Niknejad, and C. Hu, "A framework for modeling double-Gate MOSFETs," in Workshop on Compact Modeling, 2003, pp. N/A.
• J. He, X. Xi, M. Chan, A. Niknejad, and C. Hu, "An advanced surface-potential-plus MOSFET model," in Workshop on Compact Modeling, 2003, pp. N/A.
• M. V. Dunga, X. Xi, J. He, I. Polishchuk, Q. Lu, M. Chan, A. Niknejad, and C. Hu, "Modeling of direct tunneling current in multi-layer gate stacks," in Workshop on Compact Modeling, 2003, pp. N/A.
• A. Niknejad, M. Chan, C. Hu, X. Xi, J. He, P. Su, Y. Cao, H. Wan, M. V. Dunga, C. Doan, S. Emami Neyestanak, and C. Lin, "Compact modeling for RF and microwave applications (Invited)," in Workshop on Compact Modeling, 2003, pp. N/A.
• C. Lin, J. He, X. Xi, H. Kam, A. Niknejad, M. Chan, and C. Hu, "The impact of scaling on volume inversion in symmetric double-gate MOSFETs," in Semiconductor Device Research Symposium, 2003, pp. 148-149.
• C. Lin, P. Su, Y. Taur, X. Xi, J. He, A. Niknejad, M. Chan, and C. Hu, "Circuit performance of double-gate SOI CMOS," in Semiconductor Device Research Symposium, 2003, pp. 266-267.
• P. Su, S. Fung, P. Wyatt, H. Wan, M. Chan, A. Niknejad, and C. Hu, "A unified model for partial-depletion and full depletion SOI circuit designs: Using BSIMPD as a foundation," in Proceedings of CICC, 2003, pp. N/A.
• S. Lam, H. Wan, P. Su, P. Wyatt, C. Chen, A. Niknejad, C. Hu, P. Ko, and M. Chan, "RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology," IEEE Electron Device Letters, vol. 24, pp. 251-253, April 2003.
• P. Su, S. Fung, P. Wyatt, W. Hui, A. Niknejad, M. Chan, and C. Hu, "On the body-source built-in potential lowering of SOI MOSFETs," IEEE Electron Device Letters, vol. 24, pp. 90-92, Feb. 2003.
• P. Su, S. Fung, H. Wan, A. Niknejad, M. Chan, and C. Hu, "An impact ionization model for SOI circuit simulation," in IEEE International SOI Conference, 2002, pp. 201-202.
• B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
• Y. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. King Liu, J. Bokor, and C. Hu, "Paul Rappaport Award for 2002: Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 279-286, Feb. 2002.
• Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide, Boston, MA: Kluwer Academic Publishers, 1999.
• K. F. Schuegraf and C. Hu, "Reliability of thin SiO2," Semiconductor Science and Technology, vol. 9, no. 5, pp. 989-1004, May 1994.
• C. Hu, "IC reliability simulation," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 241-246, March 1992.