

Robert K. Brayton
Professor Emeritus, Professor in the Graduate School
Research Areas
Research Centers
Biography
Robert Brayton received the BSEE degree from Iowa State University in 1956 and the Ph.D. degree in mathematics from MIT in 1961. He was a member of the Mathematical Sciences Department of the IBM T. J. Watson Research Center until he joined the EECS Department at Berkeley in 1987. He held the Edgar L. and Harold H. Buttner Endowed Chair and is currently the Cadence Distinguished Professor of Electrical Engineering at Berkeley. He is a member of the National Academy of Engineering, and a Fellow of the IEEE and the AAAS. He received the 1991 IEEE CAS Technical Achievement Award, the 1971 IEEE GuillemanCauer award, the 1987 ISCAS Darlington award. In 2000, he received the 2000 CAS Golden Jubilee and the IEEE Millennium Medals, the 2002 Iowa State University Marston Medal, and in 2006, the IEEE Emanuel R. Piore, the ACM Kanallakis and the EDAA Lifetime Achievement Awards. In 2007 he received the EDAC/CEDA Phil Kaufman Award and in 2009, the SIGDA/CEDA A. Richard Newton Technical Impact Award. He has authored over 450 technical papers, and 10 books in the areas of the analysis of nonlinear networks, simulation and optimization of electrical circuits, logic synthesis, and formal design verification.
Selected Publications
 A. Mishchenko, S. Chatterjee, and R. K. Brayton, "Improvements to technology mapping for LUTbased FPGAs," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 240253, Feb. 2007.
 J. R. Jiang and R. K. Brayton, "Retiming and resynthesis: A complexity perspective," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 26742686, Dec. 2006.
 S. Chatterjee, A. Mishchenko, R. K. Brayton, X. Wang, and T. Kam, " Reducing structural bias in technology mapping," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 29842903, Dec. 2006.
 A. Mishchenko, S. Chatterjee, and R. K. Brayton, "DAGaware AIG rewriting: A fresh look at combinational logic synthesis," in Proc. IEEE/ACM 43rd Annual Conf. on Design Automation, New York, NY: ACM Press, 2006, pp. 532535.
 A. Mishchenko and R. K. Brayton, "A theory of nondeterministic networks," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 977999, June 2006.
 A. Mishchenko, J. S. Zhang, S. Sinha, J. R. Burch, R. K. Brayton, and M. ChrzanowskaJeske, "Using simulation and satisfiability to compute flexibilities in Boolean networks," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 743755, May 2006.
 Y. Li, A. Kondratyev, and R. K. Brayton, "Gaining predictability and noise immunity in global interconnects," in Proc. 5th Intl. Conf. on Application of Concurrency to System Design, Los Alamitos, CA: IEEE Computer Society, 2005, pp. 176185.
 A. Mishchenko and R. K. Brayton, "SATbased complete don'tcare computation for network optimization," in Proc. Design, Automation and Test in Europe, Vol. 1, Los Alamitos, CA: IEEE Computer Society, 2005, pp. 412417.
 J. R. Jiang and R. K. Brayton, "Functional dependency for verification reduction," in Computer Aided Verification: Proc. 16th Intl. Conf. (CAV 2004), R. Alur and D. A. Peled, Eds., Lecture Notes in Computer Science, Vol. 3114, Berlin, Germany: SpringerVerlag, 2004, pp. 268280.
 S. P. Khatri, S. Sinha, R. K. Brayton, and A. L. SangiovanniVincentelli, "SPFDbased wire removal in standardcell and networkofPLA circuits," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 23, no. 7, pp. 10201030, July 2004.
 F. Mo and R. K. Brayton, "A timingdriven modulebased chip design flow," in Proc. 2004 41st Design Automation Conf., New York, NY: ACM Press, 2004, pp. 6770.
 Y. Jiang, S. Matic, and R. K. Brayton, "Generalized cofactoring for logic function evaluation," in Proc. 2003 40th Design Automation Conf., Piscataway, NJ: IEEE Press, 2003, pp. 155158.
 N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko, and A. L. SangiovanniVincentelli, "Equisolvability of series vs. controller's topology in synchronous language equations," in Proc. 6th Design, Automation and Test in Europe Conf. and Exhibition (DATE 2003), N. Wehn and D. Verkest, Eds., Los Alamitos, CA: IEEE Computer Society, 2003, pp. 11541155.
 M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. SangiovanniVincentelli, "HW/SW Partitioning and Code Generation of Embedded Control Applica tions on a Reconfigurable Architecture Platform," in Proceedings of the tenth international symposium on Hardware/software codesign, 2002.
 M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. SangiovanniVincentelli, "HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform," in Proc. 10th Intl. Symp. on Hardware/Software Codesign (CODES 2002), New York, NY: ACM Press, 2002, pp. 151156.
 R. K. Brayton, "Compatible observability don't cares revisited," in IEEE/ACM Intl. Conf. on Computer Aided Design (ICCAD 2001). Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2001, pp. 618623.
 R. K. Brayton, G. D. Hachtel, A. L. SangiovanniVincentelli, F. Somenzi, A. Aziz, S. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa, "VIS: A system for verification and synthesis," in Lecture Notes in Computer Science: Computer Aided Verification, R. Alur and T. A. Henzinger, Eds., Vol. 1102, London, UK: SpringerVerlag, 1996, pp. 428432.
 E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. SangiovanniVincentelli, "Sequential circuit design using synthesis and optimization," in Proc. IEEE 1992 Intl. Conf. on Computer Design: VLSI in Computers and Processors, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 328333.
 R. K. Brayton, G. D. Hachtel, and A. L. SangiovanniVincentelli, "Invited Paper: Multilevel logic synthesis," Proc. IEEE, vol. 78, no. 2, pp. 264300, Feb. 1990.
 R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. SangiovanniVincentelli, Logic Minimization Algorithms for VLSI Synthesis, The Kluwer International Series in Engineering and Computer Science, Vol. 2, Boston, MA: Kluwer Academic Publishers, 1984.



