Krste Asanović

Associate Professor

Research Areas

• Computer Architecture & Engineering (ARC)
• Design of Electronic Systems (DES)
• Integrated Circuits (INC)
• Operating Systems & Networking (OSNT)

Teaching Schedule (Spring 2008)

• CS 152. Computer Architecture & Engineering, T T 2:00-3:30P, 320 Soda
• CS 298-44. Topics in Manycore Processor Design, TH 11:00-12:30P, 373 Soda

Selected Publications

• K. Asanovic, "Invited Paper: Transactors for parallel hardware and software co-design," in Proc. IEEE Intl. High Level Design Validation and Test Workshop (HLDVT-2007), 2007, pp. 3 pp..
• J. W. Lee, M. King, and K. Asanovic, "Continual hashing for efficient fine-grain state inconsistency detection," in Proc. 25th IEEE Intl. Conf. on Computer Design (ICCD-2007), Los Alamitos, CA: IEEE Computer Society, 2007, pp. 8 pp..
• S. Heo, R. Krashinsky, and K. Asanovic, "Activity-sensitive flip-flop and latch selection for reduced energy," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 9, pp. 1060-1064, Sep. 2007.
• R. Krashinsky, C. Batten, and K. Asanovic, "Winner, DAC/ISSCC Student Design Contest: The scale vector-thread processor," in Proc. 45th Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 3 pp..
• J. Wawrzynek, D. A. Patterson, M. Oskin, S. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanovic, "RAMP: Research Accelerator for Multiple Processors," IEEE Micro, vol. 27, no. 2, pp. 46-57, March 2007.
• K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The Landscape of Parallel Computing Research: A View from Berkeley," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-183, Dec. 2006.
• K. Asanovic, J. L. Hennessy, and D. A. Patterson, "Appendix F: Vector Processors," in Computer Architecture: A Quantitative Approach, 4 ed., Boston, MA: Morgan Kaufmann Publishers, 2006.
• S. Crago, J. McMahon, C. Archer, K. Asanovic, R. Chaung, K. Goolsbey, M. Hall, C. Kozyrakis, K. Olukotun, U. O'Reilly, R. Pancoast, V. Prasanna, R. Rabbah, S. Ward, and D. Yeung, "CEARCH: Cognition Enabled Architecture," in Proc. 10th Workshop on High Performance Embedded Computing (HPEC), Defense Technical Information Center, 2006, pp. 25 pp..
• K. C. Barr and K. Asanovic, "Energy-aware lossless data compression," ACM Trans. Computer Systems, vol. 24, no. 3, pp. 250-291, Aug. 2006.
• M. Hampton and K. Asanovic, "Implementing virtual memory in a vector processor with software restart markers," in Proc. 20th Annual Intl. Conf. on Supercomputing (ICS06), New York, NY: The Association for Computing Machinery, Inc., 2006, pp. 135-144.
• J. W. Lee and K. Asanovic, "METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors," in Proc. 12th IEEE Real-Time and Embedded Technology and Applications Symp. (RTAS 2006), S. Goddard and J. Liu, Eds., Los Alamitos, CA: IEEE Computer Society Press, 2006, pp. 135-147.
• R. F. Liu and K. Asanovic, "Accelerating architectural exploration using canonical instruction segments," in Proc. 2006 IEEE Intl. Symp. on Performance Analysis of Systems and Software, Piscataway, NJ: IEEE, 2006, pp. 13-24.
• K. C. Barr and K. Asanovic, "Branch trace compression for snapshot-based simulation," in Proc. 2006 IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS 2006), Piscataway, NJ: IEEE, 2006, pp. 25-35.
• G. Gibeling, A. Schultz, and K. Asanovic, "The RAMP architecture & description language," in Proc. 2nd Workshop on Architecture Research Using FPGA Platforms (WARFP 2006), 2006, pp. 4 pp..
• C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lei, "Unbounded transactional memory," IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences, pp. 59-69, Jan. 2006.
• H. Pan, K. Asanovic, R. Cohn, and C. Luk, "Controlling program execution through binary instrumentation," ACM SIGARCH Computer Architecture News Special Issue: WBIA '05, vol. 33, no. 5, pp. 45-50, Dec. 2005.
• E. Witchel, J. Rhee, and K. Asanovic, "Mondrix: Memory isolation for Linux using Mondriaan Memory Protection," ACM SIGOPS Operating Systems Review, vol. 39, no. 5, pp. 31-44, Dec. 2005.
• S. Heo and K. Asanovic, "Replacing global wires with an on-chip network: A power analysis," in Proc. 2005 Intl. Symp. on Low Power Electronics and Design (ISLPED '05), New York, NY: The Association for Computing Machinery, Inc., 2005, pp. 369-374.
• M. Zhang and K. Asanovic, "Victim replication: Maximizing capacity while hiding wire delay in tiled CMPs," in Proc. 32nd Intl. Symp. on Computer Architecture (ISCA-32), Los Alamitos, CA: IEEE Computer Society, 2005, pp. 336-345.
• J. H. Tseng and K. Asanovic, "A speculative control scheme for an energy-efficient banked register file," IEEE Trans. Computers, vol. 54, no. 6, pp. 741-751, June 2005.