Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Cory-Soda Hall Logo
photo of Krste Asanović
   

Krste Asanović

Professor

Research Areas

Research Centers

Teaching Schedule (Fall 2014)

Selected Publications

  • M. Maas, P. Reames, J. Morlan, K. Asanović, A. D. Joseph, and J. D. Kubiatowicz, "GPUs as an Opportunity for Offloading Garbage Collection," in Proceedings of the 2012 International Symposium on Memory Management, ISMM '12, New York, NY, USA: ACM, 2012, pp. 25--36.
  • A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2011-62, May 2011.
  • B. C. Catanzaro, S. A. Kamil, Y. Lee, K. Asanović, J. Demmel, K. Keutzer, J. Shalf, K. A. Yelick, and A. Fox, "SEJITS: Getting productivity and performance with selective embedded JIT specialization," in Proceedings First Workshop on Programming Models for Emerging Architectures, 2009.
  • C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanović, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics," IEEE Micro, vol. 29, July 2009.
  • S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanovic, "Designing Multi-socket Systems Using Silicon Photonics," in Proceedings 23rd International Conference on Supercomputing, 2009.
  • A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamin, K. Asanović, and V. Stojanovic, "Silicon-Photonic Clos Networks for Global On-Chip Communication," in 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009.
  • C. Jones, R. Liu, L. Meyerovich, K. Asanović, and R. Bodik, "Parallelizing the Web Browser," in First USENIX Workshop on Hot Topics in Parallelism, 2009.
  • R. Liu, K. Klues, S. Bird, S. Hofmeyr, K. Asanović, and J. D. Kubiatowicz, "Tessellation: Space-Time Partitioning in a Manycore Client OS," in First USENIX Workshop on Hot Topics in ParallelismH, 2009.
  • H. Pan, B. Hindman, and K. Asanović, "Lithe: Enabling Efficient Composition of Parallel Libraries," in First USENIX Workshop on Hot Topics in Parallelism, 2009.
  • C. Batten, H. Aoki, and K. Asanović, "The case for malleable stream architectures," in Workshop on Streaming Systems, 2008.
  • C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, "Building manycore processor-to-DRAM networks with monolithic silicon photonics," in Proc. 16th Annual IEEE Symp. on High-Performance Interconnects (HotI 2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 21-30.
  • S. C. Miller, M. M. Deneroff, C. F. Schimmel, L. Rudolph, C. E. Leiserson, B. C. Kuszmaul, and K. Asanović, "System and method for performing memory operations in a computing system," U.S. Patent 7,398,359. July 2008.
  • R. Krashinsky, C. Batten, and K. Asanovic, "Implementing the Scale vector-thread processor," ACM Trans. Design Automation of Electronic Systems, vol. 13, no. 3, pp. Art. 41:1-24, July 2008.
  • J. W. Lee, M. C. Ng, and K. Asanovic, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in Proc. 35th Intl. Symp. on Computer Architecture (ISCA 2008), Los Alamitos, CA: IEEE Computer Society, 2008, pp. 89-100.
  • M. Hampton and K. Asanovic, "Compiling for vector-thread architectures," in Proc. 6th Annual IEEE/ACM Intl. Symp. on Code Generation and Optimization (CGO-2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 205-215.
  • K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2008-23, March 2008.
  • K. Asanović, "Vector Processing," in Digital Systems and Applications, V. G. Oklobdzija, Ed., 2nd ed., The Computer Engineering Handbook, Boca Raton, FL: CRC Press, 2007, pp. 1-25-1-35.
  • K. Asanovic, "Transactors for parallel hardware and software co-design (Invited Paper)," in Proc. 2007 IEEE Intl. High Level Design Validation and Test Workshop (HLDVT-2007), Los Alamitos, CA: IEEE Computer Society, 2007, pp. 140-142.
  • K. Asanovic and E. J. Witchel, "System and technique for fine-grained computer memory protection," U.S. Patent 7,287,140. Oct. 2007.
  • J. W. Lee, M. King, and K. Asanovic, "Continual hashing for efficient fine-grain state inconsistency detection," in Proc. 25th IEEE Intl. Conf. on Computer Design (ICCD 2007), Piscataway, NJ: IEEE Press, 2007, pp. 33-40.