EE 290B. Advanced Topics in Solid State Devices
Current Schedule (Spring 2016)
In this course we will analyze the major roadblocks standing in the path of further progress in digital nano-electronics. We start by acknowledging the culmination of conventional "critical-dimension" scaling in the semiconductor ITRS roadmap. Therefore it appears justified that there may emerge a new scaling paradigm based on power. Some limits on energy efficiency for logic operations, memory operations, and communications, will be derived. The apparent major obstacle appears to be the excess signal-to-noise ratio that is designed into conventional digital electronics. This is dictated by the fact that the universal switch, the transistor, is thermally activated, and requires a high voltage >>kT/q~1Volt to operate well. On the other hand the wires in a circuit would have tolerable signal-to-noise ratio operating even at 1 mVolt. This manifests itself as a factor ~10^6 inefficiency in current digital electronics.
We will project some anticipated technical options that could eventually eliminate this million-fold factor:
- solid-state switching devices, that operate in the milli-Volt regime.
- nano-transistor options with steeper sub-threshold slope.
- nano-optical links.
- novel nano-scale impedance matching transformers, including plasmonics.
- new forms of amplification using giant magneto-resistance, and other spintronic effects.
- nano-mechanical switching elements that are capable of very low voltage operation.
- low-temperature electronics.
- electro-chemical switching elements.
The goal of the course is to anticipate which device option would most likely represent the future of digital electronics.