EE 141/241A. Introduction to Digital Integrated Circuits
Current Schedule (Fall 2014)
CMOS devices and deep sub-micron manufacturing technology. CMOS inverters and complex gates. Modeling of interconnect wires. Optimization of designs with respect to a number of metrics: cost, reliability, performance, and power dissipation. Sequential circuits, timing considerations, and clocking approaches. Design of large system blocks, including arithmetic, interconnect, memories, and programmable logic arrays. Introduction to design methodologies, including hands-on experience. The labs will cover the full ASIC chip design flow, from Verilog RTL, to synthesis, place and route, to post-layout extraction and verification.