Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

Joint Colloquium Distinguished Lecture Series


Analog Mixed-Signal Circuits in Advanced Nano-scale CMOS Technology for Microprocessors and SoCs

Ian Young

Wednesday, September 8, 2010
306 Soda Hall (HP Auditorium)
4:00 - 5:00 pm

Ian A. Young
Senior Fellow, Director Advanced Circuits / Exploratory ICs., Technology and Manufacturing Group, Intel Corporation

Downloadable pdf

Abstract:

High performance microprocessors have relied on increasing levels of analog circuits since the phase locked loop (PLL) was integrated to increase performance from de-skewing the on-chip clock distribution and enabling higher frequency clocking, hugher than the system clock. Delay locked loops (DLL) for CPU I/O to memory, LC-PLLs for high speed serial I/O (at > 5Gb/s), band-gap reference based thermal temperature sensors to manage the CPU temperature through clock throttling, and 10b linear DACs for video display have been monolithically integrated with digital CMOS optimized for the microprocessor. The unique challenge for the analog designer of these circuits has been the decreasing power supply voltage each generation that was needed to support MOS device scaling and which was accelerated by the need for reduced power consumption. However the difficulty in implementing these circuits was undertaken because of the significant performance improvements that they enabled for the microprocessor. Thus, with the increasing analog content, the microprocessor has transformed and become more like an SoC design. While the scaling of digital CMOS continued beyond the 90nm node, where strained silicon was first introduced into the MOS transistor, more complex analog circuits were added to the microprocessor with the integration of high speed serial I/O. At the 45nm and 32nm CMOS nodes the analog circuits were being designed at the unprecedented power supply voltage of 1.0V with strained silicon and high k metal gate transistors while maintaining silicon area scaling not just for digital circuits but also for analog circuits. The 45nm and 32nm nano-scale CMOS transistors have required the analog designer to innovate and develop new analog circuit architectures, in particular those using more digital circuits to “assist” the analog circuit by means of calibration and adaption. While there were challenges from the deeply scaled nano-CMOS transistors for analog circuits there were benefits of high bandwidth (ft) and lower power.  Transistors with halo doping for short channel control and high-k metal gate enabled improvement in the inverse area sensitivity of threshold voltage variations. The metal gate transistor meant that salicide or polysilicon resistors were no longer available but newly introduced process elements for the digital CMOS were adopted instead. 

Recently the SoC has become the frontier for continuing Moore’s Law by providing ever more integration on the integrated circuit. In the SoC process based on a deeply nano-scale digital CMOS there are many attributes to leverage. For example low noise amplifiers can achieve the low noise figure required for wireless communications through the use of the high ft (>300GHz) 32nm transistors and the power distribution thick metal layers for inductors. A few process features such as precision resistor and high resistance wafer are added to enhance the performance of circuit functions such RF circuits and high speed I/O. The SoC based on advanced nano-scale digital CMOS can provide the density, low power and analog and RF integration capability needed for the high volume and small form factor applications of the future.

Examples of key analog mixed-signal circuit functional blocks implemented in advanced 45nm and 32nm logic CMOS on microprocessors and SOCs will be presented.

Biography

Ian A. Young is a Senior Fellow and the Director of Exploratory Integrated Circuits, in Intel’s Components Research for the Technology and Manufacturing Group, in Hillsboro, Oregon. He is responsible for identifying leading options for devices and interconnects to manufacture the solid-state integrated circuit in the post CMOS era.

Dr. Young joined Intel in 1983. Starting from development of circuits for a 1Megabit DRAM, he led the design of three generations of SRAM products and manufacturing test vehicles, and developed the original Phase Locked Loop (PLL) based clocking circuit in a microprocessor for the 50MHz Intel486™ processor. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel processors through the 0.13um 3.2 GHz Pentium 4, enabling them to leverage transistor speed improvements. This innovative clock circuit was one of the key factors for his promotion to Intel Fellow in 1996. Young has developed a number of optimization metrics for technology development, including the transistor performance metric (FEM) that provided a link between processor performance and basic transistor parameters. He has led a circuit design team doing research and development of mixed-signal circuits for microprocessor and SOC products with the development of Intel’s advanced process technology. For 45nm, 32nm and 22nm CMOS this team developed mixed-signal high speed serial I/O circuits for microprocessor I/O and 32nm CMOS wireless RF CMOS synthesizers and transceiver circuits for SOCs. He has driven research enabling Optical I/O for chip to chip interconnect. 

Born in Melbourne, Australia, he received his bachelor's and master's degrees in Electrical Engineering from the University of Melbourne, Australia. He received his Ph.D. in Electrical Engineering from the University of California, Berkeley. 

Dr. Young is a Fellow of the IEEE.  He has authored or co-authored over 40 technical papers.


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