EECS Joint Colloquium Distinguished Lecture Series

Wednesday, December 8, 2004
Hewlett Packard Auditorium, 306 Soda Hall
4:00-5:00 p.m.

Dr. Peter Hofstee

IBM Microelectronics Division


Microprocessor Design Tradeoffs




This talk reassesses advances in processor architecture in light of metrics that recognize power efficiency as the fundamental limiter to performance. We propose that in the light of these metrics many of the "advances" have been steps in the wrong direction, and we propose alternatives that can increase processor performance while simultaneously improving power efficiency.


Peter Hofstee received his Ph.D. in computer science from the Caltech in 1995. In 1995 and 1996 he was on the faculty at Caltech. In 1996 he joined the IBM Austin Research Laboratory where he worked on the world's first 1GHz CMOS integer microprocessor (ISSCC 1998). In 2001 Dr. Hofstee was one of the founding members of the joint Sony-Toshiba-IBM design center in Austin to develop the next generation of microprocessors for the broadband era.