EECS Joint Colloquium Distinguished Lecture Series

Wednesday, April 7, 2004
430-438 Soda Hall, Wozniak Lounge
1:00-2:30 p.m.

M.S. Degree from UCLA

Electrical Engineering and Computer Science Dept.,
University of California, Berkeley


A/D Interface Design for Future Digital Radios: An Adoptive Filtering Approach




In low-cost, highly integrated digital communication receiver systems-on-a-chip, the boundary between analog and digital worlds is constantly redefined as a result of CMOS technology advancement. The superior scalability of digital VLSI circuits, coupled with the trend toward more digital signal-processing for receiver programmability and multi-standard agility, continuously advances the digitization interface toward antenna. Meanwhile, the lack of high-Q, on-chip channel-select filtering in these receivers inevitably leads to a large dynamic-range requirement on the analog-to-digital interface circuit at the presence of close-in interferers. High-performance, low-power A/D interface design under low supply voltages in nanometer CMOS technology has become a keen challenge for future digital radios, heralded by the emergence of ultra-wideband radio, cognitive radio, and radio that uses multiple antennas.

In this talk, I will introduce a digital background calibration approach for Nyquist ADCs based on the concept of adaptive filtering. In this approach, analog circuit impairments are modeled as distortions in digital communication channels. It follows that efficient error corrections can be achieved by performing adaptive equalization in the digital domain, allowing inaccurate but simple, wideband, and power-efficient analog circuits to be used in these interfaces. Therefore, strong tradeoffs between speed and accuracy in precision analog designs are much relaxed and the “digital” approach enables it to benefit from CMOS technology scaling as opposed to most conventional techniques.


Yun Chiu holds a B.S. degree in physics from the University of Science and Technology of China and an M.S. degree in electrical engineering from UCLA. He is currently an EECS Ph.D. candidate. From 1997 to 1999, he was with PixArt Technology Inc., where he designed CMOS ICs for digital imaging products. His current research interests include high-performance, low-power, and low-voltage baseband interface designs for wireless and wireline communications, and adaptive digital signal-processing techniques for enhancing the performance of analog and mixed-signal circuits. He was a recipient of the Foreign Scholar award from UCLA, the Regents’ Fellowship of UCB, the Intel Ph.D. Fellowship, and the Cal View Teaching Fellow award.