Challenges in Circuits, Design and Devices for Low Power SoC

EECS Joint Colloquium Distinguished Lecture Series

pic of Toshi Masuhara

Dr. Toshiaki Masuhara
Senior Chief Engineer, Hitachi Corporation

Wednesday, August 30, 2000
Hewlett Packard Auditorium, 306 Soda Hall
4:00-5:00 p.m.


The CMOS is entering an era of Deep-Sub-Micro (DSM) and System-on-a-Chip(SoC). In this talk, challenges of the technology for the future CMOS is first reviewed. New CMOS technology direction requires the new logic, buffering and threshold control circuit techniques and design methodologies in the future CMOS SoC. These will be discussed based on the recent ISSCC talks and panels and the other Conference talks.


Toshiaki Masuhara obtained the B.S. and M.S. Degrees in Electrical Engineering from the University of Kyoto, Japan in 1967 and 1969. He obtained the Ph.D. Degree in Electrical Engineering from the University of Kyoto in 1977. In 1969, he became a member of the technical staff at the Hitachi Central Research Laboratory, where he initially worked on depletion-load NMOS integrated circuits and later on modeling and analysis of MOS transistors. In 1974-75, he was a special student in the Electrical Engineering and Computer Science Department of the University of California, Berkeley, where he worked on double-diffused MOS transistors and a new CMOS process. In the ensuing years, he initiated a project to develop new high speed CMOS static memories with NMOS cells, supervised research groups working on high speed GaAs and bipolar integrated circuits, solar cells, and imager tubes, and was responsible for the design of VLSIs, components and PCBs. In 1993 Dr. Masuhara became General Manager of Technology Development Operation, and in 1977 he became General Manager of the Semiconductor Manufacturing Technology Center. He became Senior Chief Engineer in 1998.

Dr. Masuhara is a Fellow of IEEE (From 1994, with the citation "For Contribution in the invention and development of NMOS circuits and high-speed CMOS static memories," and a member of the Institute of Electrical, Information and Communication Engineers of Japan. He has been an administrative committee member of the Solid-State Circuits Society of IEEE since 1998. He was the program co-chair and chairman of the 1992 and 1993 Symposium on VLSI Circuits and was the co-chair and the chairman of the 1996 and 1997 Symposium on VLSI Circuits. He received 1990 IEEE Solid-State Circuits Award on his contributions to NMOS depletion-load circuits and the development of high speed CMOS memories. From 2000, he is a chairman of the Semiconductor Technology Roadmap Committee of Japan. He has received a Significant Invention Award, Japan, in 1994, four Significant Invention Awards, Tokyo, Japan in 1984, 1985, 1988 and 1992, Significant Invention Awards, Yamanashi, Japan, in 1995 and Gunma, Japan, in 1996.