GSRC logo Gigascale Systems Research Center

Location: 2108 Allston Way, suite 200 and 550 Cory Hall
Time: 2:00 - 5:00 PM

"Electronic systems design in the late- and post-silicon age"

With semiconductor technology reaching the nanometer scale in approximately 15 years, concerns such as complexity, power, variability and reliability are forcing major shifts in design paradigms. More specifically, the GSRC see the following major trends:
Massively parallel, programmable architectures will make major inroads in integrated circuits for both computational infrastructure and peripheral devices, inspired by power and time-to-market concerns.

The challenges of parameter variability and circuit reliability are best addressed by allocating an increasing number of transistors to the tasks of dynamic on-line tuning and providing error-resiliency. Ultimately, it probably will lead to computational models that are substantially different from those that are in vogue today.

Each of the above strategies addresses a particular problem, such as power, concurrency, variability or reliability, and integrates aspects from multiple communities (such as modeling, exploration, synthesis, verification, and test). To do this successfully requires a common design technology framework for complex heterogeneous systems which can be shared over technology domains and optimization targets.

Addressing these challenges requires innovative and disruptive solutions. By bringing the best minds in US academia (41 faculty from 17 institutions) together in a collaborative and forward-looking setting, the GSRC led by the University of California at Berkeley with Professor Jan Rabaey and Ken Lutz as directors, is uniquely positioned to deliver some of the answers. The GSRC’s previous track record has demonstrated that this model ("not research as usual") is highly effective in producing ground-breaking results.