Berkeley EECS Annual Research Symposium 2006 February 23, 2006
Electrical Enginnering and Computer Science College of Engineering, UC Berkeley










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Speaker Abstracts

The Future of Correct Software - George Necula

It is estimated that software bugs cost the economy almost 1% of GDP, even without considering the damages incurred when a bug is exploited for security breaches. This talk gives an overview of several software engineering technologies and tools being developed by our Open Source Quality research group for the purpose of assisting programmers to construct and deploy correct software, to find errors in existing software, and to deal with errors that arise after deployment. We will discuss "Programming by Sketching", a technique where programmers write a simple, but perhaps inefficient, version of the code, along with hints for a high-performance implementation. A compiler can then fill-in the complex details of the high-performance implementation. Another technique, "Cooperative Bug Isolation", identifies likely programming bugs by using statistical analysis of many small pieces of information obtained from actual runs of the software deployed at many customer sites. Finally, "Proof-Carrying Code" enables the deployment of correct software even between parties that do not have a preexisting trust relationship. The software is accompanied by an easy-to-check proof attesting that the software has the required correctness or security properties. By checking the attached proof, the code receiver can certify easily and with certainty that the code has correctness properties that would be impossible to ascertain by inspection of the code alone.

The Future of Computer Architecture - David Patterson

The past of computer architecture has been innovating in compilers, instruction sets, and microarchitectures to make faster sequential computers. The future of computer architecture is in

  • identifying the numerical methods that will be important in the future

  • creating "auto-tuners" for such numerical methods that will sample the computer and the data to produce code tailored to that combination

  • evaluating the next generation of computers by seeing how they improve security, privacy, usability, and reliability (SPUR) in addition to how they improve performance, cost, and power efficiency

  • using reconfigurable hardware to rapidly explore parallel hardware and software systems
    Hence, when building the next generation, computer architects will now look forward rather than backwards.

This talk will also describe a new multi-university intiative to build a low-cost, research-oriented, massively parallel processor called RAMP, for Research Accelerator for Multiple Processors. RAMP relies on FPGAs to achieve massive parallelism at low cost by emulating the whole system at reasonable speeds. In addition, the project depends on the architecure research community to deliver logic designs for RAMP so that it benefit everyone interested in parallel or distributed computing. Our hope is that RAMP will become the standard platform for much systems research and advance development, thereby ramping up the popularity of multiple processors.