Nadathur R Satish

Fifth Year Graduate Student
Dept. of EECS, UC Berkeley
[nrsatish [at] eecs [dot] berkeley [dot] edu]
[http://www.eecs.berkeley.edu/~nrsatish]

Office 545Q Cory Hall Dept. of EECS University of California, Berkeley Berkeley, CA 94720 Ph: +1-510-847-6172

Home 1929 Delaware Street Apartment 2B Berkeley, CA 94709-2193 Ph: +1-510-845-4298

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Purpose

Looking for a summer internship at a top company/research lab.

Research Interests

Task allocation and scheduling on multi-processors, system architecture, optimization, GPU computing. I currently work on mapping parallel applications to multiprocessor architectures to optimize for throughput and/or latency.

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Education

2003-Present University of California, Berkeley Berkeley, CA

Ph.D. in Electrical Engineering (expected Dec 2008) GPA: 3.97 / 4.0

1999-2003 Indian Institute of Technology, Kharagpur India

Bachelor of Technology (Honors) in Computer Science and Engg. GPA: 9.67 / 10.00

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Work Experience

7/2003 - Present University of California, Berkeley Berkeley, CA

Graduate Student Researcher

· Automating the mapping of high-performance parallel applications onto multiprocessor systems

· Using stochastic optimization to perform static mapping in the presence of task variability

Summer of 2007 NVIDIA Incorporated Santa Clara, CA

Summer Research Intern

· Optimized different algorithms in the CUDA programming model for NVIDIA GPUs.

Summer of 2005 Stretch Incorporated Mountain View, CA

Summer Research Intern

· Explored a flow from Matlab descriptions to the Stretch processor

Summer of 2001 National Semiconductor Corporation Munich, Germany

Summer Intern

· Worked as a summer intern for developing a SystemC simulator for a new chip

· Collaborated with hardware designers to develop cycle accurate simulations

· Tested the SystemC simulator with a Spec test suite

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Selected Awards and Honors

2003 Electrical Engineering Graduate Fellowship, UC Berkeley 2003
2003 President of India Gold medal for graduating at the top of the 2003

batch at IIT Kharagpur

2002 Charubala Devi Memorial Award for topping the junior batch
1999 Named in the inaugural Aditya Birla Scholarship list in 1999 –

awarded each year to 10 IIT students in India.
1998 Selected to the National Mathematical Olympiad

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Advanced Coursework at the University of California at Berkeley

Introduction to Parallel Computation CS267

Graduate Computer Architecture CS252

Field-Programmable Gate Arrays CS294-3

Logic Synthesis EE219B

Combinational Optimization IEOR264
Embedded Software Design EE249

Programming Language Design CS263

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Publications

1. A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors, Nadathur Satish, Kaushik Ravindran and Kurt Keutzer, Proceedings of the 10^th International Conference on Design Automation and Test in Europe (DATE 07), pp 57-62, April 2007
2. Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling, Jike Chong, Nadathur Rajagopalan Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, Proceedings of 2007 International Conference on Multimedia and Expo, pp 1874-1877, July 2007
3. An Automated Exploration Framework for FPGA-Based Soft Multiprocessor Systems, Yujia Jin, Nadathur Satish, Kaushik Ravindran and Kurt Keutzer, Proceedings of the 2005 International Conference on Hardware/Software Codesign and System Synthesis (CODES-05), pp 273-278, September 2005
4. An FPGA based soft multiprocessor system for IPv4 packet forwarding, Kaushik Ravindran, Nadathur Satish, Yujia Jin and Kurt Keutzer, Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL 2005), pp 487-492, August 2005
   
   

Other Technical Writings

Approaches to Abstraction of Word-Level Arithmetic Expressions using BMDs
Bachelors Thesis, IIT Kharagpur 2003